SLVSEW6F August   2021  – March 2024 TPS7H2211-SEP , TPS7H2211-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: CFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP Option
    8. 7.8  Switching Characteristics: All Devices
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Overvoltage Protection
      2. 9.3.2 Current Limit
      3. 9.3.3 Soft Start (Adjustable Rise Time)
      4. 9.3.4 Parallel Operation
      5. 9.3.5 Reverse Current Protection
      6. 9.3.6 Forward Leakage Current
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application 1: Cold Sparing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Capacitance
          2. 10.2.1.2.2 Enable Control
          3. 10.2.1.2.3 Overvoltage Protection
          4. 10.2.1.2.4 Soft Start Time
          5. 10.2.1.2.5 Summary
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Application 2: Protection
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Capacitance
          2. 10.2.2.2.2 Enable Control
          3. 10.2.2.2.3 Overvoltage Protection
          4. 10.2.2.2.4 Soft Start Time
          5. 10.2.2.2.5 Summary
        3. 10.2.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.3 Soft Start (Adjustable Rise Time)

An external capacitor, CSS, connected between the VOUT and SS pins, sets tSS, the soft start time. tSS is defined as the time it takes VOUT to rise from 10% to 90% of its final value. Equation 13 calculates the needed CSS capacitor where ISS is the soft start current (typically 65 μA) and VOUT is the final output voltage reached (for example, 12 V).

Equation 5. GUID-B21EA23D-FD64-4031-947E-AC66D842340C-low.png

In order to avoid false trips due to the internal current limit being triggered during startup, the slew rate VOUTSR, must satisfy Equation 15 where IL_trip is the internal current limit trip point (typically 8.5 A), IOUT is the final output current (max of 3.5 A), and COUT is the output capacitance. In the Application and Implementation Soft Start Time section, a suggested derated value for IL_TRIP is shown.

If external current limit circuitry is used, it is recommended to replace the IL_trip value with the minimum trip-point value of the external current limit (assuming this trip-point is less than IL_trip). This is in order to ensure the external current limit circuitry isn't tripped during startup.

Equation 6. GUID-88D3220D-0BD4-4A0E-B3F6-2DC1447446D0-low.png

The output slew rate of the eFuse, VOUTSR, can be calculated as shown in Equation 14. To determine the worst case slew rate, it is recommended to use the maximum value of ISS, 83 μA, and the minimum value of the selected capacitor. These worst case conditions may also be used to calculate the worst case (fastest) tSS time.

Equation 7. GUID-7D22E873-5513-4D53-9596-EDB78DBC3023-low.png