SLVSEW6F August   2021  – March 2024 TPS7H2211-SEP , TPS7H2211-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: CFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP Option
    8. 7.8  Switching Characteristics: All Devices
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Overvoltage Protection
      2. 9.3.2 Current Limit
      3. 9.3.3 Soft Start (Adjustable Rise Time)
      4. 9.3.4 Parallel Operation
      5. 9.3.5 Reverse Current Protection
      6. 9.3.6 Forward Leakage Current
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application 1: Cold Sparing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Capacitance
          2. 10.2.1.2.2 Enable Control
          3. 10.2.1.2.3 Overvoltage Protection
          4. 10.2.1.2.4 Soft Start Time
          5. 10.2.1.2.5 Summary
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Application 2: Protection
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Capacitance
          2. 10.2.2.2.2 Enable Control
          3. 10.2.2.2.3 Overvoltage Protection
          4. 10.2.2.2.4 Soft Start Time
          5. 10.2.2.2.5 Summary
        3. 10.2.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.4.1 Layout Guidelines

For best performance, make all traces as short as possible. Place the input and output capacitors close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Use wide traces for VIN, VOUT, and GND to help minimize the parasitic electrical effects. Pay particular attention to minimizing the length of the CSS capacitor connection between VOUT and SS in order to minimize stray inductance.

Use thermal vias for the thermal pad to ensure the device remains at allowable temperatures, especially during fault conditions (such as a short at VOUT). As the thermal pad is internally connected to GND, TI recommends the vias be connected to a large GND plane on the printed circuit board.