SLVSCJ5C December   2015  – September 2024 TPS7H3301-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT/VO Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD/VIN Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VIN Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
  10.   Power Supply Recommendations
  11. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  12. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  13.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision B (June 2020) to Revision C (September 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Electrical characteristics are tested in ambient conditions of -55ºC to 125ºC, previous reference to TJ is updated to TA Go
  • VTTSNS test condition to show -5mA test condition and updated limits; additional VTTSNS test conditions and limits at 5mA and -1A to 1AGo
  • Clarified specification name VLDOIN-VTT/VO to VDO, removed Note1Go
  • Production testing coverage for VDO (VLDOIN-VTT/VO) implemented across temperature, Note 2 has been removed for test conditions previously appended with Note 2 Go
  • Updated IVOSCRL limits and test conditions for IVOSRCL and IVOSNCL Go
  • Production testing coverage of RDSCHRG implemented across temperatureGo
  • Clarified test condition description for VTH(PG) Go
  • Removed VDDQSNS voltage range from Electrical Characterisitics table as this is contained in the Recommended Operating Conditions tableGo
  • Updated VVTTREF name to VVTTREF(load_reg) and added new accuracy spec, VVTTREFaccuracy Go
  • Clarified test conditions for IVTTREFSRCL & IVTTREFSNCCL Go
  • VVINUVVIN tested across temperatureGo
  • IENLEAK tested across temperatureGo
  • Removed Note for TSON, note is redundant for typical specificationsGo
  • Revised reference to 100kΩ pull-up resistorGo
  • Updated power dissipation calculation for VDD/VIN and VLDOINGo

Changes from Revision A (June 2016) to Revision B (June 2020)

  • Changed DLA drawing number Go
  • Changed radiation performance feature summary Go
  • Changed feature description for supported DDR termination applications Go
  • Changed VTTREF accuracy feature Go
  • Changed description of supported DDR applications Go
  • Added package weight to Device Information tableGo
  • Changed pin name references throughout document to be consistent Go
  • Added additional thermal metricsGo
  • Added clarification of TJ temperature range in Electrical Characteristics tableGo
  • Changed ambiguous tolerance specification for VTT/VO to explicitly specify min/max rangeGo
  • Changed UVLO threshold hysteresis to own table entry Go
  • Changed naming on VTTREF plots for consistency Go
  • Added ceramic to capacitor description to meet stability requirementsGo
  • Added correct cross reference for output current limitGo
  • Changed wording for clarity for VIN/VDD Go
  • Changed comment to reflect total ESR Go
  • JEDEC specification references Go
  • Changed to improved transient plot and descriptionGo
  • Added or smaller for layout thermal via size Go
  • Changed to improved recommended layout diagram. Go