SLVSEN7D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
  • KGD|0
  • HKY|34
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.8 Compensation Component Selection

There are several industry techniques used to compensate DC-DC regulators. For this design, type 2B compensation is used as shown in the Small Signal Model for Frequency Compensation section.

A good starting rule of thumb is to set the crossover frequency to one-tenth of the switching frequency. This will generally provide good transient response and ensure that the modulator poles do not degrade phase margin.

The compensation components can be calculated using Equation 19 and Equation 21. The values calculated for R3 and C1 are 8.66 kΩ and 12 nF, respectively.

An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R3 and C1. The pole frequency is given by Equation 33.

Equation 33. GUID-8A6B71AF-0C79-4BF6-AE23-D5A55AC4BB96-low.gif