SLVSF07F July   2021  – August 2024 TPS7H5001-SP , TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5001-SP
    7. 7.7  Electrical Characteristics: TPS7H5002-SP
    8. 7.8  Electrical Characteristics: TPS7H5003-SP
    9. 7.9  Electrical Characteristics: TPS7H5004-SP
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFT|22
  • KGD|0
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.9 RCD Clamp

A resistor-capacitor-diode clamp circuit can be used to limit the voltage at the switch node. The equations below can be used to determine initial values for the resistor and capacitor, but the circuit will need to be optimized through testing. First, calculate the clamp voltage by determining how much overshoot is allowable at the switch node.

Equation 57. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

The parameter KCLAMP defines the target overshoot value. For example, set KCLAMP to 1.5 for 50% allowable overshoot.

Next, the leakage inductance LL and peak primary current IPRI_MAX of the transformer can be used to approximate the clamp resistor. The clamp capacitor value can be determined thereafter. Note that ΔVCLAMP defines the allowable ripple for the clamp capacitor.

Equation 58. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
Equation 59. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP