SLVSF07F July   2021  – August 2024 TPS7H5001-SP , TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5001-SP
    7. 7.7  Electrical Characteristics: TPS7H5002-SP
    8. 7.8  Electrical Characteristics: TPS7H5003-SP
    9. 7.9  Electrical Characteristics: TPS7H5004-SP
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFT|22
  • KGD|0
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.17 Slope Compensation (RSC)

When utilizing peak current mode control in switching power converter design, the converter can enter into an unstable state when the duty cycle for the main power switch rises above 50%. Essentially, the converter will be in a state where the error between the peak current and average current increases with each subsequent switching cycle. This instability, known as subharmonic oscillation, can be mitigated by adding slope compensation. For the TPS7H500x-SP, the slope compensation is in the form of a voltage ramp that is subtracted from the error amplifier output divided down by the parameter CCSR (COMP to CS_LIM ratio). The minimum slope compensation for stability over the entire duty cycle range is equal to 0.5 × m, where m is the inductor falling current slope. The recommended slope compensation is 1 × m, as any increase above this value will not improve stability.

For a typical buck converter, setting the slope compensation equal to the downward slope of the sensed current waveform yields the calculation in Equation 16.

Equation 16. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

where:

  • SC is the slope compensation value in V/μs
  • L is the output inductor value in μH
  • NCSP is the number of primary turns of the current sense transformer
  • NCSS is the number of secondary turns on the current sense transformer
  • RCS is the value of the current sense resistor in Ω

If no current sense transformer is used, set NCSP / NCSS to 1.

The slope compensation for the forward converter will be similar with the note that the sensed current waveform would also need to take into account the turns ratio of the main power transformer.

Equation 17. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

where:

  • NS is the number of secondary turns of the power transformer
  • NP is the number of primary turns of the power transformer

For the TPS7H500x-SP controllers, a resistor from the RSC pin to AVSS can be used to set the desired slope compensation. Equation 18 shows the calculation for determining the proper resistor value for RSC.

Equation 18. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

where:

  • SC is the desired slope compensation is V/μs
  • RSC is in kΩ