SLVSGG1A February   2022  – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5005-SEP
    7. 7.7  Electrical Characteristics: TPS7H5006-SEP
    8. 7.8  Electrical Characteristics: TPS7H5007-SEP
    9. 7.9  Electrical Characteristics: TPS7H5008-SEP
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA/SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 TPS7H5005-SEP PW Package
24-Pin TSSOP
(Top View)
Figure 6-3 TPS7H5007-SEP PW Package
24-Pin TSSOP
(Top View)
Figure 6-2 TPS7H5006-SEP PW Package
24-Pin TSSOP
(Top View)
Figure 6-4 TPS7H5008-SEP PW Package
24-Pin TSSOP
(Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME TPS7H5005-SEP TPS7H5006-SEP TPS7H5007-SEP TPS7H5008-SEP
RT 1 1 1 1 I/O In internal oscillation mode, the RT pin must be populated with a resistor to AVSS. When the RT pin is floating, a 200-kHz to 4-MHz external clock is required at the SYNC pin. The frequency of the external clock must be twice the desired switching frequency.
PS 2 2 — — I/O Primary off to synchronous rectifier on dead-time set. Programmable through an external resistor to AVSS.
SP 3 3 — — I/O Synchronous rectifier off to primary on dead-time set. Programmable through an external resistor to AVSS.
LEB 4 4 — 4 I/O Leading edge blank time set. Programmable through an external resistor to AVSS.
HICC 5 5 5 5 I/O Cycle-by-cycle current limit time delay and hiccup time setting. Delay time and hiccup time determined by capacitor from HICC to AVSS. Connecting this pin to AVSS disables hiccup mode.
SYNC 6 6 6 6 I/O When the RT pin is floating, SYNC is configured as an input for a 200-kHz to 4-MHz external clock. In this case, the external clock input gets inverted and the system clock will run at half the frequency of the external clock input. When the RT pin is populated with a resistor to AVSS, SYNC outputs a 200-kHz to 4-MHz clock signal at twice the device switching frequency in phase with the switching of the device.
DCL 7 7 7 7 I/O Duty cycle limit configurability. For TPS7H5005-SEP, connect to AVSS for 50% duty cycle limit, floating for 75%, and VLDO for 100%. For TPS7H5006-SEP and TPS7H5007-SEP, the DCL pin can be left floating or connected to VLDO to set the maximum duty cycle to 75% or 100%, respectively. For TPS7H5008-SEP, this pin must be connected to AVSS in order to obtain the 50% maximum duty cycle.
EN 8 8 8 8 I Connecting the EN pin to the VLDO pin or external source greater than 0.6 V enables the device. In addition, input undervoltage lockout (UVLO) can be adjusted with two resistors.
VIN 9 9 9 9 I Input supply to the device. Input voltage range is from 4 V to 14 V.
OUTA 10 10 10 10 O Primary switching output A.
OUTB 11 — — 11 O Primary switching output B. Active only when DCL = AVSS.
SRB 14 — — — O Synchronous rectifier output B. Active only when DCL = AVSS.
SRA 15 15 15 — O Synchronous rectifier output A.
AVSS 16 16 16 16 — Ground of the device.
VLDO 17 17 17 17 O Output of internal regulator. Requires at least 1-μF external capacitor to AVSS.
CS_ILIM 18 18 18 18 I/O Current sense for PWM control and cycle-by-cycle overcurrent protection. An input voltage over 1.05 V on CS_ILIM will trigger an overcurrent in the PWM controller. The sensed waveform on CS_ILIM contains a 150-mV offset when compared to the COMP/2 voltage at the input of the PWM comparator.
FAULT 19 19 19 19 I Fault protection pin. When the rising threshold of the FAULT pin is exceeded, the outputs will stop switching. After the external voltage drops below the falling threshold, the device will restart after a set delay. Connect this pin to AVSS to disable FAULT.
REFCAP 20 20 20 20 O 1.2-V internal reference. Requires a 470-nF external capacitor to AVSS.
RSC 21 21 21 21 I/O A resistor from RSC to AVSS sets the desired slope compensation.
SS 22 22 22 22 I/O Soft start. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
VSENSE 23 23 23 23 I Inverting input of the error amplifier.
COMP 24 24 24 24 I/O Error amplifier output. Connect frequency compensation to this pin.
NC 12, 13 11, 12, 13, 14 2, 3, 4, 11, 12, 13, 14 2, 3, 12, 13, 14, 15 — No connect. Can be connected to AVSS to avoid floating metal if desired.