SLVSGG1A February   2022  – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5005-SEP
    7. 7.7  Electrical Characteristics: TPS7H5006-SEP
    8. 7.8  Electrical Characteristics: TPS7H5007-SEP
    9. 7.9  Electrical Characteristics: TPS7H5008-SEP
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA/SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics: All Devices

TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGES AND CURRENTS
VIN Operating input voltage 4 14 V
IDD Operating supply current fSW = 500 kHz, No load for OUTA, OUTB, SRA, and SRB 6.25 8 mA
fSW = 1 MHz, No load  for OUTA, OUTB, SRA, and SRB 6.75 9.5
fSW = 2 MHz, No load for OUTA, OUTB, SRA, and SRB 8.5 13.5
fSW = 500 kHz, CLOAD = 100 pF for OUTA, OUTB, SRA, and SRB 7.5 9.5
fSW = 1 MHz, CLOAD = 100 pF for OUTA, OUTB, SRA, and SRB 9 12
fSW = 2 MHz, CLOAD = 100 pF for OUTA, OUTB, SRA, and SRB 14 19.5
IDD(dis) Standby current EN = 0 V 3 mA
VLDO Internal linear regulator output voltage 5 V ≤ VIN ≤ 14 V, fsw ≤ 1 MHz 4.75 5 5.2 V
VLDO Internal linear regulator output voltage 5 V ≤ VIN ≤ 14 V, fsw = 2 MHz 4.65 5 5.2 V
ENABLE AND UNDERVOLTAGE LOCKOUT
VENR EN threshold rising 0.57 0.6 0.65 V
VENF EN threshold falling 0.47 0.5 0.55 V
VENH EN hysteresis voltage 85 95 105 mV
IEN EN pin input leakage current VIN = 14 V, EN = 5 V 5 50 nA
VLDOUVLOR VLDO UVLO rising 3.44 3.55 3.66 V
VLDOUVLOF VLDO UVLO falling 3.29 3.4 3.51 V
VLDOUVLOH VLDO UVLO hysteresis 115 135 160 mV
SOFT START
ISS Soft-start current SS = 0.3 V 1.98 2.7 3.32 µA
ERROR AMPLIFIER
EAgm Transconductance –2 µA < ICOMP < 2 µA, V(COMP) = 1 V 1150 1800 2500 µA/V
EADC DC gain VSENSE = 0.6 V 10000 V/V
EAISRC Error amplifier source current V(COMP) = 1 V, 100-mV input overdrive 100 190 µA
EAISNK Error amplifier sink current V(COMP) = 1 V, 100-mV input overdrive 100 190 µA
EAro Error amplifier output resistance 7 MΩ
EAOS Error amplifier input offset voltage –2 2 mV
EAIB Error amplifier input bias current 35 nA
EABW Bandwidth 10 MHz
OSCILLATOR
SYNCIL SYNC in low-level VIN < 5 V 0.8 V
VIN ≥ 5 V 0.8
SYNCIH SYNC in high-level VIN < 5 V 3.5 V
VIN ≥ 5 V 3.5
FSYNC SYNC in frequency range   200 4000 kHz
DSYNC SYNC in duty cycle Duty cycle of external clock 40 60 %
SYNCRT SYNC out low-to-high rise time (10%/90%) CLOAD = 25 pF 6 15 ns
SYNCFT SYNC out high-to-low fall time (10%/90%) CLOAD = 25 pF 6 17 ns
SYNCOL SYNC out low level  IOL = 10 mA 500 mV
VLDO – SYNCOH SYNC out high level (1) IOH = 10 mA 0.5 V
EXTDT Externally set frequency detection time RT = Open, f = 200 kHz 20 µs
FSWEXT Externally set frequency RT = 1.07 MΩ 95 105 115 kHz
RT = 511 kΩ 190 210 230
RT = 90.9 kΩ 900 1000 1100
RT = 34.8 kΩ 1700 2000 2300
VOLTAGE REFERENCE
VREF Internal voltage reference initial tolerance  Measured at COMP, 25°C 0.609 0.613 0.615 V
Internal voltage reference  Measured at COMP, –55°C 0.607 0.609 0.612
Measured at COMP, 125°C 0.611 0.614 0.617
REFCAP REFCAP voltage REFCAP = 470 nF 1.213 1.225 1.237 V
CURRENT SENSE, CURRENT LIMIT AND HICCUP
CCSR COMP to CS_ILIM ratio 2.00 2.06 2.12
VCS_ILIM Current limit (overcurrent) threshold 1.05 1.09 V
IHICC_DEL Hiccup delay current CS_ILIM = 1.3 V, COMP = 3 V, VSENSE =  REFCAP/2 V, CHICC = 3 nF, LEB = 49.9 kΩ, fsw = 100 kHz 80 µA
IHICC_RST Hiccup restart current 1 µA
VHICC_PU Hiccup pull-up threshold 1.0 V
VHICC_SD Hiccup shut-down threshold 0.6 V
VHICC_RST Hiccup restart threshold 0.3 V
SLOPE COMPENSATION
Slope compensation fSW = 100 kHz, RSC = 1.18 MΩ 0.033 V/µs
fSW = 200 kHz, RSC = 562 kΩ 0.066
fSW = 1000 kHz, RSC = 100 kΩ 0.333
fSW = 2000 kHz, RSC = 49.9 kΩ 0.666
FAULT
VFLTR FLT threshold rising 0.57 0.6 0.65 V
VFLTF FLT threshold falling 0.47 0.5 0.55 V
VFLTH FLT hysteresis voltage 90 100 110 mV
TFLT FLT minimum pulse width VFLT = 1 V 0.4 1.4 µs
tDFLT FLT delay duration fsw = 100 kHz 140 152 169 µs
fsw = 200 kHz 66 78 86
fsw = 1 MHz 14 17 21
fsw = 2 MHz 7 11 14
THERMAL SHUTDOWN
Thermal shutdown 165 175 185 °C
Thermal shutdown hysteresis 10 15 20 °C
PRIMARY AND SYNCHRONOUS RECTIFIER OUTPUTS
Low-level threshold ISINK = 10 mA 0.5 V
High-level threshold ISOURCE = 10 mA 4.5 V
Rise/fall time RLOAD = 50 kΩ, CLOAD = 100 pF, 10% to 90% 10 17 ns
RSRC_P Output source resistance IOUT = 20 mA, 5 V ≤ VIN ≤ 14 V 15 Ω
RSINK_P Output sink resistance IOUT = 20 mA, 5 V ≤ VIN ≤ 14 V 15 Ω
(1) Bench verified.  Not tested in production.