SLVSGG1A February   2022  – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5005-SEP
    7. 7.7  Electrical Characteristics: TPS7H5006-SEP
    8. 7.8  Electrical Characteristics: TPS7H5007-SEP
    9. 7.9  Electrical Characteristics: TPS7H5008-SEP
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA/SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

In order to increase the reliability of the converter design using the TPS7H500x-SEP, the following layout guidelines should be followed.

  • Route the feedback trace as far away as possible from power magnetics components (inductor and/or power transformer) and other noise inducting traces on the printed circuit board (PCB) such as the switch node. If the feedback trace is routed beneath the power magnetic component, ensure that this trace is on another layer of the PCB with at least one ground layer separating the trace from the inductor or transformer.
  • Minimize the copper area of the converter switch node for the best noise performance and reduction of parasitic capacitance to reduce switching losses. Ensure that any noise sensitive signals, such as the feedback trace, are routed away from this node as it contains a high dv/dt switching signal.
  • All high di/dt and dv/dt switching loops in the power stage should have the paths minimized. This will help to reduce EMI, lower stresses on the power devices, and reduce any noise coupling into the control loop.
  • Keep the analog ground of the controller (AVSS) separate from the power ground of the power stage that contains high frequency, high di/dt currents. These two grounds should be connected at a single point in the PCB layout. The sources of power semiconductor switches, the returns for bulk input capacitors of the power stage, and the ouput capacitor return should all be connected to the PCB power ground.
  • All high current traces on the PCB should be short, direct, and as wide as possible. A good rule is to make the traces a minimum of 15 mils (0.381 mm) per ampere.
  • Place all filtering and bypass capacitors for VIN, REFCAP, and VLDO as close as possible to the controller. Surface mount ceramic capacitors with lower ESR and ESL are recommended as these reduce the potential for noise coupling compared to through-hole capacitors. Care should be taken to minimize the loop area formed by the bypass capacitor connection, the respective pin, and AVSS. Each bypass capacitor should have a good, low impedance connection to AVSS.
  • External compensation components should be placed near the COMP pin of the controller. Surface mount components are recommended here as well.
  • Attempt to keep the resistor divider used to generate the voltage at VSENSE close to the device in order to reduce noise coupling. Minimize stray capacitance to the VSENSE pin.
  • OUTA, OUTB, SRA, and SRB are used to drive the inputs of a gate driver, isolator, or gate drive transformer. The PCB traces connected to these pins carry high dv/dt signals. Reduce noise coupling by routing these these PCB traces away from any traces connected to VSENSE, COMP, RT, CS_ILIM, HICC, LEB, RSC, PS, and SP.
  • In addition to utilizing the leading edge blank time programmability of the controller, RC filtering may be required for the sensed current signal input to CS_ILIM. Keep the resistor and capacitor in close vicinity to CS_LIM to filter any ringing and/or spikes that may be present on the sensed current signal.
  • When operating in internal oscillator mode with SYNC as an output, route the SYNC signal away from noise sensitive signals/pins such as VSENSE, COMP, RT, CS_ILIM, LEB, RSC, PS, and SP. Special care should be taken to eliminate noise from SYNC to HICC since these pins are adjacent to one another. It is recommended that the capacitor from HICC to AVSS be at least 3.3 nF to help with the reduction of the noise.