SBVS445A October   2024  – December 2024 TPS7N53

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Power-Good Pin (PG Pin)
      6. 6.3.6 Active Discharge
      7. 6.3.7 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Disabled
      3. 6.4.3 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 7.1.3  Recommended Capacitor Types
      4. 7.1.4  Soft-Start (SS Pin) and Noise Reduction (NR Pin)
      5. 7.1.5  Charge Pump Noise
      6. 7.1.6  Optimizing Noise and PSRR
      7. 7.1.7  Adjustable Operation
      8. 7.1.8  Load Transient Response
      9. 7.1.9  Power-Good Functionality
      10. 7.1.10 Paralleling for Higher Output Current and Lower Noise
      11. 7.1.11 Power Dissipation (PD)
      12. 7.1.12 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.12 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 10 and are given in the Section 5.5 table.

Equation 10. TPS7N53

where:

  • PD is the power dissipated as explained in Equation 7
  • TT is the temperature at the center-top of the device package
  • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge