SBVS445A October   2024  – December 2024 TPS7N53

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Power-Good Pin (PG Pin)
      6. 6.3.6 Active Discharge
      7. 6.3.7 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Disabled
      3. 6.4.3 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 7.1.3  Recommended Capacitor Types
      4. 7.1.4  Soft-Start (SS Pin) and Noise Reduction (NR Pin)
      5. 7.1.5  Charge Pump Noise
      6. 7.1.6  Optimizing Noise and PSRR
      7. 7.1.7  Adjustable Operation
      8. 7.1.8  Load Transient Response
      9. 7.1.9  Power-Good Functionality
      10. 7.1.10 Paralleling for Higher Output Current and Lower Noise
      11. 7.1.11 Power Dissipation (PD)
      12. 7.1.12 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.4 Soft-Start (SS Pin) and Noise Reduction (NR Pin)

The TPS7N53 has an SS pin and an NR pin to independently control the soft-start time and reducing the noise generated by the internal band-gap reference and the external resistor RREF.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an external capacitor (CSS). In addition to the soft-start feature, the CNR capacitor lowers the output voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to the input power bus.

To achieve a monotonic start up, the device output voltage tracks the VNR reference voltage until this reference reaches the set value (the set output voltage). The VNR reference voltage is set by the RREF resistor and, during start up, the device uses a fast charging current (ISS), as shown in Figure 7-2, to charge the CSS capacitor.

Note: Any leakage on the NR and REF pins directly impacts the accuracy of the reference voltage.
TPS7N53 Simplified Soft-Start Circuit Figure 7-2 Simplified Soft-Start Circuit

The 30μA (typical) ISS current quickly charges CSS until the voltage reaches approximately 90% of the set output voltage, then the ISS current turns off, the switch between NR and SS closes, as well as the switch between NR and REF.

Note: The discharge pulldown resistor on NR and SS (see the Functional Block Diagram) is engaged when any of the GND referenced UVLOs have been tripped, or when any faults occur (overtemp, PORs, IREF bad, or OTP error) and the NR, SS pin voltages are above 50 mV.

The soft-start ramp time depends on the fast start-up (ISS) charging current, the reference current (IREF), CSS capacitor value, and the targeted output voltage (VOUT(target)). Equation 4 calculates the soft-start ramp time.

Equation 4. Soft-start time (tSS) = (VOUT(target) × CSS) / ( ISS)

The ISS current is provided in the Section 5.5 and has a value of 30μA (typical). The IREF current has a value of 150μA (typical). The remaining 10% of the start-up time is determined by the RREF × CNR time constant.

The output voltage noise can be lowered significantly by increasing the CNR capacitor. The CNR capacitor and RREF resistor form a low-pass filter (LPF) that filters out noise from the VREF voltage reference, thereby reducing the device noise floor. The LPF is a single-pole filter and Equation 5 calculates the LPF cutoff frequency. Increasing the CNR capacitor can significantly lower output voltage noise. For low-noise applications, use a 1μF or larger CNR for optimal noise.

Equation 5. Cutoff Frequency (fcutoff) = 1 / (2 × π × RREF × CNR)
Note: Current limit can be entered during start up with a small CNR and large COUT because VOUT no longer tracks the soft-start ramp.

Figure 7-3 shows the impact of the CNR capacitor on the LDO output voltage noise.

TPS7N53 Output Voltage Noise Density vs CNRFigure 7-3 Output Voltage Noise Density vs CNR