SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
Figure 7-56 shows the LH1IADJL register. Table 7-49 describes the LH1IADJL register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LH1IADJ[1:0] | ||||||
R-000000b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 000000 | Reserved |
1-0 | LH1IADJ[1:0] | R/W | 00 | Channel 1 analog current control in limp-home mode. The 2 LSBs of the 10-bit IADJ DAC for channel 1 can be programmed by writing to the register. |