SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
After the existing POR state, the device waits for an SPI transaction. If no transaction with an correct SPI frame is received for 224 system clock cycles (approximately 1.55 s), the communication watchdog timer times out and the device enters stand-alone mode of operation. Receiving a valid SPI frame before the watchdog timeout resets the timer and the device transitions to LOAD mode.