SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
Figure 7-51 shows the V5D register. Table 7-39 describes the V5D register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
V5D[7:0] | |||||||
R-00000000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | V5D[7:0] | R | 00000000 | ADC measurement of the 5-V bias supply. The V5D pin voltage is internally attenuated by 0.45 to achieve an 8-bit conversion ratio of 5.33/255 (V/dec). |