SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The ADC updates the CHxVLED register every time after sampling the CSNx input. The CSNx pin voltage is internally attenuated by 0.037 to achieve an 8-bit conversion ratio of 65/255 (V/dec). Since the sampling interval is asynchronous to the PWM operation, the logic incorporates two additional registers, CHxVLEDON and CHxVLEDOFF, to save the output voltage information based on the PWM operation. The contents of the CHxVLED register are copied to CHxVLEDON on the falling edge of the PWM signal to record the CSNx voltage when the PWM input was high. Similarly, the CHxVLED register is copied to CHxVLEDOFF on the rising edge of the PWM signal to record the CSNx voltage when the PWM input was low. This ensures the most consistent LED voltage reading during PWM operation.