SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
Figure 7-29 shows the SLEEP register. Table 7-16 describes the SLEEP register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLEEP[1:0] | ||||||
R-000000b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 000000 | Reserved |
1-0 | SLEEP | R/W | 00 | Device sleep mode. The low-power sleep mode can be activated by writing to the register. 00 = Exit sleep mode and return to normal operation (SLEEP OFF). 01 = Enter sleep mode (SLEEP ON). 10 = No effect 11 = No effect |