SLUSCX8C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
EN is the channel enable register. This register contains bits associated with the enabling of channels and several channel-related functions.
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
00h | EN | FPINRST | SYNCEN | CH2MAXDEN | CH1MAXDEN | CH2PDRVEN | CH1PDRVEN | CH2EN | CH1EN | 00111100 |
Setting this bit to one resets both fault pins, if there are no active faults in the system. Note that this bit is write-only. Any reads of this register return 0 in the FPINRST bit location.
0: SYNC input is disabled.
1: SYNC input is enabled.
0: Maximum duty cycle for the associated channel is disabled.
1: Maximum duty cycle for the associated channel is enabled.
0: The associated channel PFET driver is disabled.
1: The associated channel PFET driver is enabled.
0: The associated channel is disabled.
1: The associated channel is enabled. SPI writes of ‘1’ to these bits are blocked if the PC bit in the FLT1 register is high.