FLT1 register bits are set if a selected fault shown in Table 7-20 occurs. Reading this register clears the bits that are set, if the associated faults no longer exist. Note that the clearing of the bits happens at the end of the read response SPI transfer, not at the end of the read command SPI transfer.
Table 7-20 FLT1 Register| ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
|---|
| 11h | FLT1 | RTO | RSVD | PC | TW | CH2OV | CH1OV | CH2UV | CH1UV | read |
- RTO: RT pin is open.
- PC: Power Cycled bit; This bit is set at power up
and upon POR. Neither of the two channels can be
enabled while this bit is set. The PC bit must be
cleared before the soft-start DAC state machine
can progress and the channels can be turned on. To
clear the PC bit, FLT1 register should be read.
The clearing of the Fault-Read-bits happens at the
end of the SPI transfer read response, not at the
end of the read command.
- TW: Thermal Warning bit
- CHxOV: Output overvoltage fault (CH2OV is disabled if 2PH is set to '1').
- CHxUV: Output undervoltage fault (CH2UV is disabled if 2PH is set to '1').