SLUSCX8C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
The TPS92682-Q1 can be enabled or disabled by the EN pin or the software enable bits. When EN pin is pulled low, the device enters shutdown state, where the quiescent current of the device is decreased to IIN-SHDN. In shutdown state, the internal regulators are turned off and the registers are reset. When the voltage on the enable pin is increased above the voltage threshold of VEN, the two channels can be enabled. In addition to the EN pin, there are two enable bits for the two channels of the TPS92682-Q1 as shown in Table 7-2. In order for each channel to be turned on, the associated CHxEN bit must be set to "1" in EN Register.
In addition to the EN pin and the CHxEN bits, the PWMx signals (hardware or software) must be set high and the associated CHxIADJ must be set to a value greater than eight (refer to the CH1IADJ Register) in order for the associated channel to be turned on.