SLVSE03B April 2019 – February 2021 TPS929120-Q1
PRODUCTION DATA
The TPS929120-Q1 has two PWM inputs that can be used to directly control OUT0-11. The both ADDR1/ PWM1 and ADDR0/ PWM0 pins are multi-function pins for not only external PWM input signal but also device slave address selection pins. The register EEP_INTADDR must be written to 1 to release both twos for external PWM input. When the EEP_INTADDR is 1, the ADDR0/ PWM0 is functional as external active low PWM control input for OUT0-5 and the ADDR1/ PWM1 is functional as external active low PWM control input for OUT6-11, as shown in Figure 7-2. Setting the register CONF_PWMOUTx to 0xFF and the register CONF_PWMLOWOUTx to 0xF is recommended when external PWM input is used. In case external PWM is not used, ADDR0/ PWM0 and ADDR1/ PWM1 must be tied to GND when EEP_INTADDR is set to 1.