DLPS039G December 2015 – July 2024 TPS99000-Q1
PRODUCTION DATA
ADDRESS | NAME | BITS | DESCRIPTION |
---|---|---|---|
Chip Revision ID, R-only, Reset Value 0000 | |||
0x00 | Unused | [15:8] | Unused |
Major | [7:4] | Major revision | |
Minor | [3:0] | Minor revision | |
Status Set, R/W, Reset Value 0000 (Writing a 1 to any bit field sets flag) | |||
0x01 | PG Fault Status | [15] | Asserted when any bin in user register 38h is set |
DM Max width limit | [14] | Maximum DM pulse width achieved. This may or may not be an error, depending on system operational mode | |
VXPG Init | [13] | Power good timer for VOFS, VRST, or VBIAS expired | |
Main SPI parity error | [12] | Parity error on a SPI1 port transaction occurred (command or write data) on previous command | |
ADC block error | [11] | "OR" of all errors in ADC block. Refer to x0D to determine specific error. | |
Checksum error 3 | [10] | Checksum error in LED / dimming controller section | |
Checksum error 2 | [9] | Checksum error in light sensor conditioning section | |
Checksum error 1 | [8] | Checksum error in ADC sub-system section | |
WD2 | [7] | Watchdog #2 error | |
WD1 | [6] | Watchdog #1 error | |
Top level state change | [5] | Indicates top level state machine has changed state. Can be used to indicate that the TPS99000-Q1 has exited DISPLAY state unexpectedly due to a random fault | |
Excessive brightness | [4] | Excessive brightness detector indicates an over bright fault condition | |
VXPG Fault | [3] | Set 1 by hardware if power good fault occurs for VOFS, VRST, or VBIAS | |
DIE Over temp warning | [2] | Thermal conditions on chip have reached the warning level. If temperature continues to rise, system will reach die over temp error temperature and emergency actions will be taken by TPS99000-Q1 | |
DIE Over temp error | [1] | Thermal conditions on chip have reached the emergency/error. Emergency actions will be taken by TPS99000-Q1 to protect the system. This error bit is non-maskable for PARKZ output | |
PROJ_ON_LOW | [0] | Projector ON input pin is low (produces a 1 on this status bit). | |
General Status 1, R-only, Reset Value 0000 | |||
0x05 | Clock ratio monitor | [15:12] | Mid-scale reading (1000 ± 1) indicate approximately 30-MHz external signal has been applied |
Open | [11:8] | Reserved | |
Last Reset (2:0) | [7:5] | Root cause of last reset cycle, last pass through the OFF state. “000” – true power on cycle, internal reset set/release “001” – PROJ_ON went low “010” – watchdog timer 1 error “011” – watchdog timer 2 error “100” – die over temperature error “101” – SW power cycle command all others unused | |
Top State (4:0) | [4:0] | Top level state machine current state 0x00 = SHUTDOWN 0x01 = Internal initialization 0x02 = OFF 0x03 = Internal initialization 0x04 = Initializing 1P1V 0x05 = Initializing 1P8V 0x06 = Initializing 3P3V 0x07 = De-assert RESETZ 0x08 = STANDBY 0x09 = VOFFSET enabled 0x0A = VBIAS enabled 0x0B = VRESET enabled 0x0C = DISPLAY READY 0x0D = DISPLAY ON 0x0E = Parking initialized 0x0F = VBIAS and VRESET disabled 0x10 = VOFFSET disabled 0x11 = DMD voltage discharge |