SLVSHS7 October   2024 TPSI31P1-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.1 CDIV1, CDIV2 Capacitance

The CDIV1 and CDIV2 capacitors required depends on the amount of drop that can be tolerated on the VDDH rail during switching of the external load. The charge stored on the CDIV1 and CDIV2 capacitors is used to provide the current to the load during switching. During switching, charge sharing occurs and the voltage on VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of CDIV1 and CDIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in an approximate 0.5V drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 12 and Equation 13 can be to used to calculate the amount of capacitance required for a specified voltage drop.

CDIV1 and CDIV2 must be of the same type and tolerance.

Equation 12. CDIV1=n+1n×QLOAD∆V, n≥3.0
Equation 13. CDIV2=n×CDIV1, n≥3.0

where

  • n is a real number greater than or equal to 3.0.
  • CDIV1 is the external capacitor from VDDH to VDDM.
  • CDIV2 is the external capacitor from VDDM to VSSS.
  • QLOAD is the total charge of the load from VDRV to VSSS.
  • ΔV is the voltage drop on VDDH when switching the load.
Note: CDIV1 and CDIV2 represent absolute capacitor and components selected must be adjusted for tolerances and any derating necessary to achieve the required capacitance.

Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH under-voltage lockout falling threshold (VVDDH_UVLO_F) to be reached and cause VDRV to be asserted low. Note that as the series combination of CDIV1 and CDIV2 capacitance increases relative to QLOAD, the VDDH supply voltage drop decreases, but the initial charging of the VDDH supply voltage during power up increases.

For this design, a total gate charge for switching FET is 30nC. For a ΔV = 0.5V,

Equation 14. C D I V 1 = 3 + 1 3 × 30 n C 0.5 V = 80 n F
Equation 15. C D I V 2 = 3 × 80 n F = 240 n F

To reduce ΔV further, capacitances for this design were selected as:

Equation 16. C D I V 1 = 330 n F
Equation 17. C D I V 2 = 1 µ F