SLVSHS7 October   2024 TPSI31P1-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the TPSI31P1-Q1. Some key guidelines are:

  • Component placement:
    • Place the driver as close as possible to the power semiconductor to reduce the parasitic inductance of the gate loop on the PCB traces.
    • Connect low-ESR and low-ESL capacitors close to the device between the VDDH and VDDM pins and the VDDM and VSSS pins to bypass noise and to support high peak currents when turning on the external power transistor.
    • Connect low-ESR and low-ESL capacitors close to the device between the VDDP and VSSP pins.
    • Minimize parasitic capacitance on the RESP pin.
  • Grounding considerations:
    • Limit the high peak currents that charge and discharge the transistor gates to a minimal physical area. This limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors. Place the gate driver as close as possible to the transistors.
    • Connect the driver VSSS to the Kelvin connection of MOSFET source or IGBT emitter. If the power device does not have a split Kelvin source or emitter, connect the VSSS pin as close as possible to the source or emitter terminal of the power device package to separate the gate loop from the high power switching loop.
  • EMI considerations:

    The TPSI31P1-Q1 employs spread spectrum modulation (SSM), and in some systems, no additional system design considerations are required to meet the EMI performance needs. However, the system designer may choose to take additional measures to minimize EMI depending on the system requirements and safety preferences of the system designer. The measures listed below reduce emissions by providing a capacitive return path from the secondary side to the primary side or by increasing the common mode loop impedance with an inductive component on the primary side.

    • Inductive components: A pair of ferrite beads or a common mode choke with a high frequency impedance on the order of TBD kΩ can be placed in series with VDDP supply and VSSP ground.
    • Capacitive components: Most system designs already employ discrete Y capacitors or contain an amount of parasitic Y capacitance between the high voltage and low voltage domains. If this Y capacitance is located on the same board as the TPSI31P1-Q1, they act as a capacitive return path.
  • High-voltage considerations:
    • To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the driver device. TI recommends a PCB cutout or groove to prevent contamination that can compromise the isolation performance.
  • Thermal considerations:
    • Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-board thermal impedance (θJB).
    • If the system has multiple layers, TI also recommends connecting the VDDH and VSSS pins to internal ground or power planes through multiple vias of adequate size. These vias must be located close to the IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high voltage planes are overlapping.