SLVSHS7 October   2024 TPSI31P1-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2 Detailed Design Procedure

The battery voltage (VBAT), link capacitance (CDC_LINK), along with the target pre-charge time determines the average charging current (IAVG) required. This may be computed as follows:

Equation 1. I A V G ≥ C D C L I N K × V B A T t C H A R G E = 2 m F × 800 V   800 m s = 2 A

The average current is defined as:

Equation 2. I A V G = I P E A K + I M I N 2

The peak current, IPEAK, represents the maximum current through the inductor, and is defined by:

Equation 3. I P E A K = V R E F + R S E N S E

Similarly, the minimum current, IMIN, represents the minimum current through the inductor, and is defined by:

Equation 4. I M I N = V R E F - R S E N S E

Therefore, to find the shunt resistor, RSENSE, required to properly set the inductor current, the following equation can be used:

Equation 5. R S E N S E = V R E F + + V R E F - 2 I A V G = 1.23 V + 0.16 V 2 × 2 A = 348 m Ω

For this design, RSENSE was selected as 300mΩ.

The peak inductor current is computed as:

Equation 6. I P E A K = 1.23 V 300 m Ω = 4.1 A

The minimum inductor current is computed as:

Equation 7. I M I N = 0.16 V 300 m Ω = 0.53   A

The average inductor current is computed as:

Equation 8. I A V G = I P E A K + I M I N 2 = 4.1 A + 0.53 A 2 = 2.32 A  

During pre-charge, due to the hysteretic control, the switching frequency of the FET changes over time as the voltage on the link capacitance increases from fully discharged to fully pre-charged. The maximum switching frequency, fSW_MAX_FET, occurs when the voltage on the link capacitance reaches its midpoint value, VBAT/2. This occurs at half the total pre-charge time.

The minimum power transfer of the TPSI31P1-Q1 is limited to 42mW at 85 °C. Since the FET is switching during pre-charge, the total gate charge of the FET must be fully charged and discharged each switching cycle. This minimum power transfer constrains the maximum frequency the TPSI31P1-Q1 can switch the FET. The FET selected has a total gate charge, QTOTAL, of 30nC. Assuming VGS = 15V to ensure full enhancement of the FET, the maximum switching frequency is:

Equation 9. f S W   M A X   F E T = P V G S × Q T O T A L = 42 m W 15 V × 30 n C = 93.3 k H z

Based on the maximum switching frequency, the minimum inductance, LMIN, can be computed:

Equation 10. L M I N ≥ V B A T 4 × F S W   M A X   F E T × Δ I
Equation 11. L M I N ≥ 800 V 4 × 93.3 k H z × 4.1 A - 0.53 A ≥ 600.5 μ H

For this design, two inductors connected in series with a total value of 940μH was selected which reduces the maximum switching frequency to 61.3kHz, well within the power transfer capabilities of the TPSI31P1-Q1. It is important that an inductor be chosen that can support the average and peak currents required. Higher inductor and ΔI values reduce the switching frequency and power requirements.