SLVSHS7 October   2024 TPSI31P1-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF,  CVDRV = 1nF. 50kΩ pull-up from PGOOD to VDDP.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
CMTI Common-mode transient immunity, static. |VCM| = 1000V,
VEN = 0V or VEN = 5V.		 100 V/ns
TSD Temperature shutdown VVDDP = 5V 173 ℃
TSDH Temperature shutdown hysteresis VVDDP = 5V 32 ℃
SUPPLY
IVDDP_STBY VDDP current in standby VVDDP = 5V,
EN = 0V,
CE = 0V.
Measure average current.		 25 45 µA
IVDDP VDDP average current in steady state VVDDP = 5V, EN = CE = 5V.

VVDDH in steady state,
measure IVDDP.		 37 mA
VVDDH VDDH output voltage VVDDP = 5V, EN = CE = 5V.
 16 17 18 V
VVDDM Average VDDM voltage when not sourcing current. VVDDP = 5V, EN = CE = 5V.

 		 4.8 5.0 5.2 V
SUPERVISORY
VVDDP_UV_R VDDP under-voltage threshold rising VDDP rising.
 		 3.9 4.1 4.35 V
VVDDP_UV_F VDDP under-voltage threshold falling
VDDP falling
 		 3.8 3.9 4.25 V
VVDDP_UV_HYS VDDP under-voltage threshold hysteresis 170 mV
VVDDH_UV_R VDDH under-voltage threshold rising VDDH rising. 12.3 13 13.6 V
VVDDH_UV_F VDDH under-voltage threshold falling.
 		 VDDH falling. 9.9 10.4 11 V
VVDDH_UV_HYS VDDH under-voltage threshold hysteresis.
 		 2.5 V
VVDDM_UV_R VDDM under-voltage threshold rising VDDM rising. 3.4 3.7 3.9 V
VVDDM_UV_F VDDM under-voltage threshold falling.
 		 VDDM falling. 3.1 3.4 3.7 V
VVDDM_UV_HYS VDDM under-voltage threshold hysteresis.
 		 0.3 V
DRIVER
VVDRV_H VDRV output voltage driven high VVDDP = 5V, EN = 5V.
VVDDH in steady state.
 		 16 17 18 V
VVDRV_L VDRV output voltage driven low VVDDP = 5V, EN = 0V,
VVDDH in steady state,
VDRV sinking 10mA.
 0.1 V
IVDRV_PEAK VDRV peak output current during rise VVDDP = 5V,
EN = 0V → 5V,
VVDDH in steady state,
measure peak current.

 1.5 A
VDRV peak output current during fall VVDDP = 5V,
EN = 5V → 0V,
VVDDH in steady state,
measure peak current.

 2.5 A
VACT_CLAMP Active clamp voltage when engaged. VVDDP = 0V.
Sink IVDRV = 300mA.
Measure VDRV.		 1.9 2.5 V
DIGITAL INPUT/OUTPUT
VIT_+(EN) Input threshold voltage
rising on EN.		 VVDDP = 5V 2.3 2.5 2.7 V
VIT_-(EN) Input threshold voltage
falling on EN.		 VVDDP = 5V 1.7 1.9 2.0 V
VIT_HYS(EN) Input threshold voltage
hysteresis on EN.		 VVDDP = 5V 0.5 V
VIT_+(CE) Input threshold voltage
rising on CE.		 VVDDP = 5V 2.3 2.5 2.7 V
VIT_-(CE) Input threshold voltage
falling on CE.		 VVDDP = 5V 1.7 1.9 2.0 V
VIT_HYS(CE) Input threshold voltage
hysteresis on CE.		 VVDDP = 5V 0.5 V
VOL Low level output voltage.
PGOOD

 VVDDP = 4.5V to 5.5V,
IOL = 2mA.
Output enabled.		 0.4 V
IOL Low level output current.
PGOOD

 VVDDP = 4.5V to 5.5V,
VOL = 0.4V.
Output enabled.		 -2 mA
ILKG Leakage current.
PGOOD

 VVDDP = 4.5V to 5.5V,
Output disabled.		 2 µA
REN_PULLDOWN Internal resistor pull-down on EN. VVDDP = 5V 400 500 640 kΩ
RCE_PULLDOWN Internal resistor pull-down on CE. VVDDP = 5V 400 500 640 kΩ
REFERENCE
VREF+ Peak current reference voltage.
TA = 25°C		 1.23 V
VREF- Valley current reference voltage.
TA = 25°C		 0.16 V
VREF_TOL Internal reference voltage tolerance. -1.5 1.5 %
COMPARATORS
RCMP_PULLDOWN Internal resistor pull-down.

IS+		 1.3 2.8 3.8 MΩ