SNVSCB1C December   2022  – February 2024 TPSM33615 , TPSM33625

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Output Voltage Selection
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Enable, Start-Up, and Shutdown
      6. 7.3.6  External CLK SYNC (with MODE/SYNC)
        1. 7.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 7.3.7  Switching Frequency (RT)
      8. 7.3.8  Power-Good Output Operation
      9. 7.3.9  Internal LDO, VCC and VOUT/FB Input
      10. 7.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery from Dropout
        1. 7.3.12.1 Recovery from Dropout
      13. 7.3.13 Overcurrent Protection (Hiccup Mode)
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  Power Good Signal
        9. 8.2.2.9  Maximum Ambient Temperature
        10. 8.2.2.10 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
      3. 9.1.3 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, FSW = 1000 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input voltage rising threshold Before Start-up 3.2 3.35 3.5 V
Once Operating 2.45 2.7 3 V
IQ_VIN Input operating quiescent current (non-switching)  TA = 25°C, VEN = 3.3 V, VFB = 1.5 V 1.2 µA
ISDN_VIN VIN shutdown quiescent current VEN = 0 V, TA = 25°C 0.3 µA
ENABLE
VEN_RISE EN voltage rising threshold 1.16 1.23 1.3 V
VEN_HYS EN voltage hysteresis 0.275 0.353 0.404 V
VEN_WAKE EN wake-up threshold 0.5 0.7 1 V
ILKG-EN Enable pin input leakage current VEN = VIN  = 24 V 10 nA
INTERNAL LDO VCC
VCC Internal LDO VCC output voltage VFB = 0 V, IVCC = 1 mA 3.1 3.3 3.5 V
FEEDBACK
VFB Feedback voltage TA = 25°C, IOUT = 0 A 1.0 V
VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, FSW = 200 kHz –1 +1 %
IFB Input current into FB pin Adjustable configuration, VFB = 1.0 V 10 nA
CURRENT
IL_HS High-side switch current limit (TPSM33625)  Duty cycle approaches 0% 4.2 4.9 5.5 A
IL_LS Low-side switch current limit  (TPSM33625) 2.38 2.9 3.42 A
IL_NEG Negative current limit (TPSM33625) –2 A
IPEAKMIN Minimum peak current limit  (TPSM33625) Auto mode 0.6 A
IL_HS High-side switch current limit  (TPSM33615) Duty cycle approaches 0% 2.58 3 3.42 A
IL_LS Low-side switch current limit  (TPSM33615) 1.44 1.75 2.06 A
IL_NEG Negative current limit (TPSM33615) –2 A
IPEAKMIN Minimum peak current limit (TPSM33615) Auto mode 0.4 A
IZC Zero-cross current limit  Auto mode 80 mA
VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40 %
tW Short circuit wait time ("hiccup" time before soft start)(1) 30 50 75 ms
SOFT-START
tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2 V 2 3.5 4.6 ms
POWER GOOD
PGOV PG upper threshold - rising % of VOUT setting (adjustable output) 104 108 111 %
PGUV PG lower threshold - falling
% of VOUT setting (adjustable output)
 		 89 91 94.2 %
PGHYS PG upper threshold hysteresis for OV
% of VOUT setting

 2 2.4 2.8 %
PG upper threshold hysteresis for UV
% of VOUT setting

 2 3.3 4.6 %
VIN_PG_VALID Input voltage for valid PG output RPGD_PU = 10 kΩ, VEN = 0 V 1.5 V
VPG_LOW Low level PG function output voltage 2 mA pullup to PG pin, VEN = 3.3 V 0.4 V
tPG_FLT_RISE Delay time to PG high signal 1.35 2.5 4 ms
tRESET_FILTER PGOOD deglitch delay at falling edge 25 40 75 µs
RPGD PGOOD ON resistance VEN = 3.3 V, 200 uA pullup current 100 Ω
RPGD PGOOD ON resistance VEN = 0 V, 200 uA pullup current 100 Ω
SWITCHING FREQUENCY
fSYNC_RANGE Switching frequency range by SYNC(Mode/Sync variant) 200 2500 kHz
fADJ_RANGE Switching frequency range by RT (RT variant) 200 2200 kHz
fSW_RT1 2.2 MHZ  switching frequency programmed by RT  RRT = 0 kΩ (RT pin tied to GND) 2000 2200 2300 kHz
DeltaFc Frequency increase/decrease from spread spectrum of internal oscillator DRSS ±4%
SYNCHRONIZATION
VMODE_L SYNC/MODE input voltage low level threshold 1 V
VMODE_H SYNC/MODE input voltage high level threshold 1.6 V
tPULSE_H High Duration needed to be recognized as a pulse 100 ns
tPULSE_L Low Duration needed to be recognized as a pulse 100 ns
tB Blanking of EN after rising or falling edges(1) 4 28 µs
tSYNC High/low level pulse maximum duration to be recognized as a valid clock signal 6 µs
POWER STAGE
VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch 2.1 V
tON_MIN Minimum ON pulse width(1) FPWM mode, VOUT = 1 V, IOUT = 1 A 65 75 ns
tON_MAX Maximum ON pulse width(1) HS timeout in dropout 6 9 13 µs
tOFF_MIN Minimum OFF pulse width VIN = 4 V, IOUT = 1 A 60 85 ns
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.