SNVSC83B September   2022  – February 2023 TPSM365R3 , TPSM365R6

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  System Characteristics
    7. 8.7  Typical Characteristics
    8. 8.8  Typical Characteristics: VIN = 12 V
    9. 8.9  Typical Characteristics: VIN = 24 V
    10. 8.10 Typical Characteristics: VIN = 48 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Voltage Range
      2. 9.3.2  Output Voltage Selection
      3. 9.3.3  Input Capacitors
      4. 9.3.4  Output Capacitors
      5. 9.3.5  Enable, Start-Up, and Shutdown
      6. 9.3.6  External CLK SYNC (with MODE/SYNC)
        1. 9.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 9.3.7  Switching Frequency (RT)
      8. 9.3.8  Power-Good Output Operation
      9. 9.3.9  Internal LDO, VCC UVLO, and BIAS Input
      10. 9.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 9.3.11 Spread Spectrum
      12. 9.3.12 Soft Start and Recovery from Dropout
        1. 9.3.12.1 Recovery from Dropout
      13. 9.3.13 Overcurrent Protection (OCP)
      14. 9.3.14 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 AUTO Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
      4. 9.4.4 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2  Output Voltage Setpoint
          3. 10.2.1.2.3  Switching Frequency Selection
          4. 10.2.1.2.4  Input Capacitor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  VCC
          7. 10.2.1.2.7  CFF Selection
          8. 10.2.1.2.8  Power-Good Signal
          9. 10.2.1.2.9  Maximum Ambient Temperature
          10. 10.2.1.2.10 Other Connections
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Ground and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.4.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.

TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See
GUID-C0A6EE29-1490-494E-8A4D-C5C039090D50.html#SNVSAN37962 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding and lower thermal resistance.