SNVSC83B September   2022  – February 2023 TPSM365R3 , TPSM365R6

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  System Characteristics
    7. 8.7  Typical Characteristics
    8. 8.8  Typical Characteristics: VIN = 12 V
    9. 8.9  Typical Characteristics: VIN = 24 V
    10. 8.10 Typical Characteristics: VIN = 48 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Voltage Range
      2. 9.3.2  Output Voltage Selection
      3. 9.3.3  Input Capacitors
      4. 9.3.4  Output Capacitors
      5. 9.3.5  Enable, Start-Up, and Shutdown
      6. 9.3.6  External CLK SYNC (with MODE/SYNC)
        1. 9.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 9.3.7  Switching Frequency (RT)
      8. 9.3.8  Power-Good Output Operation
      9. 9.3.9  Internal LDO, VCC UVLO, and BIAS Input
      10. 9.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 9.3.11 Spread Spectrum
      12. 9.3.12 Soft Start and Recovery from Dropout
        1. 9.3.12.1 Recovery from Dropout
      13. 9.3.13 Overcurrent Protection (OCP)
      14. 9.3.14 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 AUTO Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
      4. 9.4.4 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2  Output Voltage Setpoint
          3. 10.2.1.2.3  Switching Frequency Selection
          4. 10.2.1.2.4  Input Capacitor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  VCC
          7. 10.2.1.2.7  CFF Selection
          8. 10.2.1.2.8  Power-Good Signal
          9. 10.2.1.2.9  Maximum Ambient Temperature
          10. 10.2.1.2.10 Other Connections
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Ground and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

A. Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only.
B. See Device Comparison Table for more details. Pin 11 trimmed and factory-set for externally adjustable switching frequency RT variants only.
Figure 7-1 RDN Package, 11-Pin QFN-HR, Top View (All Variants)
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 PGOOD A Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup voltage. If not used, this pin can be left open or connected to GND.
 High = power OK, Low = power bad. PGOOD pin goes low when EN = Low.
2 EN A Precision enable input pin. High = ON, Low = OFF. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. Can be connected directly to VIN. The module can be turned off by using an open-drain or collector device to connect this pin to GND. An external voltage divider can be placed between this pin, GND, and VIN to create an external UVLO.Do not float this pin.
3 VIN P Input supply voltage. Connect the input supply to these pins. Connect a high-quality bypass capacitor or capacitors directly to this pin and GND in close proximity to the module. Refer to GUID-C0A6EE29-1490-494E-8A4D-C5C039090D50.html#GUID-C0A6EE29-1490-494E-8A4D-C5C039090D50 for input capacitor placement example.
4 VOUT P Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external output capacitors between the pin and GND.
Fixed output options are available. For fixed output variants, connect the FB pin to VOUT. Check GUID-7D622A72-9E4E-4DC7-92BC-1D87307EED57.html#GUID-7D622A72-9E4E-4DC7-92BC-1D87307EED57 for more details.
5, 6 SW P Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
7 BOOT P Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage.
8 VCC P Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.
9 FB
or
BIAS		 A Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to GND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See GUID-C0A6EE29-1490-494E-8A4D-C5C039090D50.html#GUID-C0A6EE29-1490-494E-8A4D-C5C039090D50 for a feedback resistor placement.
For a fixed output version, connect BIAS directly to VOUT pin. Do not leave open or connect to ground.
10 GND G Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
11 RT
or
MODE/SYNC		 A When the part is trimmed as the RT pin variant, the switching frequency in the part can be adjusted from 200 kHz to 2.2 MHz based on the resistor value connected between RT and GND.
When the pin is trimmed as the MODE/SYNC variant, the part can operate in user-selectable PFM/FPWM operation. In FPWM, the part can be synchronized to an external clock. Clock triggers on rising edge of applied external clock.
Do not float this pin..
A = Analog, P = Power, G = Ground