SLVSG72 September   2021 TPSM560R6H

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (VIN = 12 V)
    7. 6.7 Typical Characteristics (VIN = 24 V)
    8. 6.8 Typical Characteristics (VIN = 48 V)
    9. 6.9 Typical Characteristics (VIN = 60 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Output Voltage (FB)
      2. 7.3.2 Minimum Input Capacitance
      3. 7.3.3 Minimum Output Capacitance
      4. 7.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
      5. 7.3.5 Power Good (PGOOD)
      6. 7.3.6 Overcurrent Protection (OCP)
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Shutdown Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Power-Good Signal
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Theta JA Versus PCB Area
      2. 10.2.2 Package Specifications
      3. 10.2.3 EMI
        1. 10.2.3.1 EMI Plots
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 10-1 and Figure 10-2 show a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Connect all PGND pins together using copper plane.
  • Connect the AGND pin to the PGND copper at a single point near the pin.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Place RFBT and RFBB as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.