SLVSGL3 April 2022 TPSM63603E
PRODUCTION DATA
For this design example, use the parameters listed in Table 9-3 as the input parameters and follow the design procedures in Section 9.2.1.4.2.
Design Parameter | Value |
---|---|
Input voltage | 12 to 24 V |
Output voltage | –5 V |
Output current | 0 A to 2 A |
Switching frequency | 1 MHz |
Table 9-4 gives the selected module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation.
Reference Designator | Qty | Specification | Manufacturer(1) | Part Number |
---|---|---|---|---|
CIN1, CIN2, CIN3 | 3 | 4.7 µF, 50 V, X7R, 1210, ceramic | Taiyo Yuden | UMK325B7475KN-TR |
TDK | CGA6P3X7R1H475K250AB | |||
4.7 µF, 50 V, X7S, 1206, ceramic | Murata | GCM31CC71H475KA03K | ||
COUT1, COUT2 | 2 | 47 µF, 10 V, X7R, 1210, ceramic | Murata | GRM32ER71A476ME15L |
AVX | 1210ZC476MAT2A | |||
CVCC | 1 | 1 µF, 16 V, X7R, 0603, ceramic | Murata | GCM188R71C105KA64J |
U1 | 1 | TPSM63603E 36-V, 3-A synchronous buck module | Texas Instruments | TPSM63603ERDLR |
More generally, the TPSM63603E module is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of output capacitance.