SLVSGL3 April   2022 TPSM63603E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  System Characteristics
    7. 7.7  Typical Characteristics
    8. 7.8  Typical Characteristics — VIN = 12 V
    9. 7.9  Typical Characteristics — VIN = 24 V
    10. 7.10 Typical Characteristics — VIN = 36 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Output ON and OFF Enable (EN/SYNC) and VIN UVLO
      7. 8.3.7  Frequency Synchronization (EN/SYNC)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power-Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT and CBOOT)
      11. 8.3.11 Internal LDO, VCC Output, and VLDOIN Input
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 — 3-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
        4. 9.2.1.4 Design 2 — Inverting Buck-Boost Regulator with a –5-V Output
          1. 9.2.1.4.1 Design Requirements
          2. 9.2.1.4.2 Detailed Design Procedure
            1. 9.2.1.4.2.1 Output Voltage Setpoint
            2. 9.2.1.4.2.2 IBB Maximum Output Current
            3. 9.2.1.4.2.3 Switching Frequency Selection
            4. 9.2.1.4.2.4 Input Capacitor Selection
            5. 9.2.1.4.2.5 Output Capacitor Selection
            6. 9.2.1.4.2.6 Other Connections
            7. 9.2.1.4.2.7 EMI
              1. 9.2.1.4.2.7.1 EMI Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.11 Internal LDO, VCC Output, and VLDOIN Input

The TPSM63603E has an internal LDO to power internal circuitry. The VCC pin is the output of the internal LDO. This pin must not be used to power external circuitry. Connect a high-quality, 1-μF capacitor from this pin to AGND, close to the device pins. Do not load the VCC pin or short it to ground.

The VLDOIN pin is an optional input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity.

The LDO generates the VCC voltage from one of the two inputs: VIN or the VLDOIN input. When VLDOIN is tied to ground or below 3.1 V, the LDO is powered from VIN. When VLDOIN is tied to a voltage higher than 3.1 V, the LDO input is powered from VLDOIN. VLDOIN voltage must be lower than both VIN and 12.5 V.

The VLDOIN input is designed to reduce the LDO power loss. The LDO power loss is:

Equation 7. PLDO-LOSS = ILDO × (VIN_LDO – VVCC)

The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the same LDO output current. The VLDOIN input provides an option to supply the LDO with a lower voltage than VIN, to reduce the difference of the input and output voltages of the LDO, and reduce power loss. For example, if the LDO current were 10 mA at a certain frequency with VIN = 24 V and VOUT = 5 V. The LDO loss with VLDOIN tied to ground is:

Equation 8. 10 mA × (24 V – 3.3 V) = 207 mW

The loss with VLDOIN tied to VOUT (5 V) is:

Equation 9. 10 mA × (5 V – 3.3 V) = 17 mW

The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher percentage of the total loss. The improvement is more significant with higher switching frequency because the LDO current is higher at higher switching frequency. The improvement is more significant when VIN » VOUT because the voltage difference is higher.

Figure 8-8 and Figure 8-9 show typical efficiency waveforms with VLDOIN powered by different input voltages.

VIN = 24 V VOUT = 5 V fSW = 1 MHz
ILDO = 10 mA
Figure 8-8 Efficiency Improvements with VLDOIN (VOUT = 5 V)
VIN = 24 V VOUT = 12 V fSW = 2 MHz
ILDO = 20 mA
Figure 8-9 Efficiency Improvements with VLDOIN (VOUT = 12 V)