SLVSHK8A December 2023 – June 2024 TPSM64404 , TPSM64406 , TPSM64406E
PRODUCTION DATA
While the PG1/PG2 of the TPSM6440X resembles a standard power-good function, the functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major differences between the PG function and the normal power-good function seen in most regulators:
For dual output configuration (RCONFIG = 0 or 121 kΩ), The PG1 is an open-drain and must be tied through a resistor to an external voltage, and pulls low if the monitors on FB1 or VOSNS1 trip. The PG2 flag is configured in the same manner as PG1 and monitors the second output at either FB2 or VOSNS2.
For single-output multiphase operation (9.53 kΩ < RCONFIG < 93.1 kΩ), PG2 is re-configured as SYNC-OUT to provide a phase shifted clock to the secondary devices. In this configuration, the PG2/SYNC-OUT terminal of the primary device can be left floating for dual phase operation or tied to the SYNC pin of the secondary device for more than four-phases. For six-phase operation the PG2/SYNC-OUT pin of the secondary device is connected to the SYNC pin of the tertiary device.
FAULT CONDITION INITIATED | FAULT CONDITION ENDS (AFTER WHICH tRESET_ACT MUST PASS BEFORE RESET OUTPUT IS RELEASED) |
---|---|
FB below VRESET_UV for longer than tRESET_FILTER | FB above VRESET_UV + VRESET_HYST for longer than tRESET_FILTER |
FB above VRESET_OV for longer than tRESET_FILTER | FB below VRESET_OV – VRESET_HYST for longer than tRESET_FILTER |
Junction temperature exceeds TSD_R | Junction temperature falls below TSD_F(1) |
EN low | tEN passes after EN becomes high(1) |
VIN falls low enough so that VCC falls below VCC_UVLO - VCC_UVLO_HYST. This value is called VIN_OPERATE. | Voltage on VIN is high enough so that VCC pin exceed VCC_UVLO(1) |
The threshold voltage for the PG function is specified to take advantage of the availability of the internal feedback threshold to the PG circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96% of actual operating point. The net result is a more accurate reset function while expanding the system allowance for transient response. See the output voltage error stack-up comparison in Figure 7-11.
In addition to signaling a fault upon overvoltage detection (FB above VRESET_OV), the switch node is shut down and a small, approximately 1-mA pulldown is applied to the SW node.
The PG signal can be used for start-up sequencing of downstream regulators, as shown in the following figure, or for fault protection and output monitoring.