SLVSHK8A December   2023  – June 2024 TPSM64404 , TPSM64406 , TPSM64406E

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 1 – High-efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Thermal Design and Layout

For a DC/DC module to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The TPSM64406 module is available in a small 6.5-mm × 7.55-mm 28-pin QFN package to cover a range of application requirements. The Section 6.4 table summarizes the thermal metrics of this package with related detail provided by the Semiconductor and IC Package Thermal Metrics application note.

The 28-pin QFN package offers a means of removing heat through the exposed thermal pads at the base of the package. This design allows a significant improvement in heat sinking. Designing the PCB with thermal lands, thermal vias, and one or more grounded planes is imperative to complete the heat removal subsystem. The exposed pads of the TPSM64406 are soldered to the ground-connected copper lands on the PCB directly underneath the device package, reducing the thermal resistance to a very low value.

Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal lands to the internal and solder-side ground planes are vital to promote heat transfer. In a multilayer PCB stack-up, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only does this design provide a plane for the power-stage currents to flow, but the design also represents a thermally conductive path away from the heat-generating device.