SLVSHK8A December 2023 – June 2024 TPSM64404 , TPSM64406 , TPSM64406E
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ(VIN-ST5p0) | VIN quiescent current, single output mode | Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 5 V + 10%, TJ = 125℃ | 25 | 45 | µA | |
IQ(VIN-ST3p3) | VIN quiescent current, single output mode | Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3 V + 10%, TJ = 125℃ | 15 | 35 | µA | |
IQ(VIN-DT3p3) | VIN quiescent current, dual output mode, BIAS = 3.3 V | Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3 V + 10%, VVOSNS2 = 5 V + 10%, TJ = 125℃ | 9 | 18 | µA | |
ISD(VIN) | VIN shutdown supply current | VEN = 0 V | 1 | 8 | µA | |
UVLO | ||||||
VINUVLO(R) | VIN UVLO rising threshold | VIN rising | 3.5 | 3.80 | V | |
VINUVLO(F) | VIN UVLO falling threshold | VIN falling | 2.55 | 3 | V | |
VINUVLO(H) | VIN UVLO hysteresis | 0.735 | 0.95 | 1.25 | V | |
ENABLE | ||||||
VEN(R) | EN1/2 voltage rising threshold | EN1/2 rising, enable switching | 1.125 | 1.25 | 1.375 | V |
VEN(F) | EN1/2 voltage falling threshold | EN1/2 falling, disable switching | 0.8 | 0.9 | 1.0 | V |
VEN(H) | EN1/2 voltage hysteresis | 0.25 | 0.325 | 0.55 | V | |
VEN(W) | EN1/2 voltage wake-up threshold | 0.4 | V | |||
IEN | EN1/2 pin sourcing current post EN rising threshold | VEN1/2 = VIN = 13.5 V | 0.6 | 400 | nA | |
INTERNAL LDO | ||||||
VVCC | Internal LDO output voltage | VBIAS ≥ 3.4 V, IVCC ≤ 100 mA | 2.7 | 3.1 | 3.7 | V |
IVCC | Internal LDO short-circuit current limit | VIN = 13.5 V | 100 | 377 | 880 | mA |
VVCC(UVLO-R) | VCC UVLO rising threshold for Start-up | 3.3 | 3.5 | 3.75 | V | |
VVCC(UVLO-F) | VCC UVLO falling threshold for Shutdown | 2.3 | 2.5 | 2.7 | V | |
REFERENCE VOLTAGE | ||||||
VFB1/2 | Dual output feedback voltages in adjustable output configuration | 788 | 800 | 812 | mV | |
VFB1_so | Single Output mode FB voltage in adjustable output configuration | 788 | 800 | 812 | mV | |
IFB1/2(LKG) | FB input leakage current in dual output configuration | VFB1/2 = 0.8 V | 10 | 250 | nA | |
IFB1_so(LKG) | FB input leakage current in single output configuration | VFB = 0.8 V | 2 | 250 | nA | |
FBSel-5v0 | Voltage threshold for fixed 5.0 V setting | VCC-0.5 | V | |||
FBSel-3v0 | Resistor for fixed 3.3 V setting | 300 | Ω | |||
FBSel-ext | Minimum Thevenin Equivalent resistance of external FB divider option to select adjustable output voltage. | 4 | kΩ | |||
ERROR AMPLIFIER | ||||||
gm-S1 | EA transconductance - single output mode | VFB1 = VCOMP | 625 | 888 | 1300 | µS |
ICOMP(src) | EA source current - single output mode | VCOMP = 1 V, VFB1 = 0.4 V | 92.5 | 200 | 400 | µA |
ICOMP(sink) | EA sink current - single output mode | VCOMP = 1 V, VFB1 = 1.2 V | 94.5 | 200 | 500 | µA |
SWITCHING FREQUENCY | ||||||
fSW1(FCCM) | Switching frequency, FCCM operation | RRT = 7.15 kΩ to AGND | 1.9 | 2.1 | 2.3 | MHz |
fSW2(FCCM) | Switching frequency, FCCM operation | RRT = 39.2 kΩ to AGND | 360 | 400 | 450 | kHz |
fADJ(FCCM) | Adjustable switching frequency range | RRT resistor from 6.81 kΩ to 158 kΩ to AGND | 0.1 | 2.2 | MHz | |
fSS(int) | Spread Spectrum switching frequency range | RRT = 7.15 kΩ, RCONFIG= 73.2 k Ω | 10% | |||
SYNCHRONIZATION | ||||||
VIH(sync) | SYNCIN High-level threshold | 1.35 | 1.6 | V | ||
VIL(sync) | SYNCIN Low-level threshold | 0.65 | 0.95 | V | ||
VOH(sync) | Sync output high voltage minimum | 10 mA load | 1.6 | 2.6 | V | |
VOL(sync) | Sync output low voltage maximum | 10 mA load | 0.34 | 0.68 | V | |
fSYNC-2p1 | Frequency sync range around 2.1 MHz | RRT = 7.15 kΩ to AGND | 1.7 | 2.1 | 2.4 | MHz |
fSYNC-0p4 | Frequency sync range around 400 kHz | RRT = 39.2 kΩ to AGND | 320 | 400 | 480 | kHz |
tSYNC(min) | Minimum pulse width of external synchronization signal above VIH(sync) | 100 | ns | |||
tSYNC(max) | Minimum width of low external synchronization signal below VIL(sync) | 100 | ns | |||
tSYNC-SW(delay) | Delay from SYNC rising edge to SW rising edge - single output mode - secondary | 90 | 130 | ns | ||
STARTUP | ||||||
tSS(R) | Internal fixed soft-start time - dual output mode | From VVOSNS1/2= 0% (first SW pulse) to VVOSNS1/2 = 90% | 2.7 | 4.5 | 7 | ms |
tSS_Lockout(R) | Time from first SW1/2 pulse to enable FPWM mode if output not in regulation - dual output mode | 7 | 13 | 32 | ms | |
ISS(R) | Soft-start charge current - single output mode | VSS = 0 V | 15 | 20 | 25 | µA |
RSS(F) | Soft-start discharge resistance - single output mode | 10 | 27 | Ω | ||
tEN | EN1 (Single output mode) or EN1/EN2 (whichever first in dual output mode) HIGH to start of switching delay | 687 | 900 | µs | ||
POWER STAGE | ||||||
RDSON(HS) | High-side MOSFET on-resistance | VBOOT-SW = 3.3 V, IOUT = 1 A | 37 | 75 | mΩ | |
RDSON(LS) | Low-side MOSFET on-resistance | VVCC = 3.3 V, IOUT = 1 A | 23.9 | 50 | mΩ | |
tON(min) | Minimum ON pulse width | VIN = 20 V, IOUT = 2 A | 40 | 62 | ns | |
tON(max) | Maximum ON pulse width (dual output, single output primary) | RRT = 7.15 kΩ | 5 | 8 | 12 | µs |
tON(max) | Maximum ON pulse width (Single output secondary) | RRT = 7.15 kΩ | 16 | 25 | µs | |
tOFF(min) | Minimum OFF pulse width | VIN = 4 V | 70 | 110 | ns | |
OVERCURRENT PROTECTION | ||||||
IHS(OC1) | High-side peak current limit TPSM64404 | Peak current limit on HS FET when Duty Cycle approaches 0% | 4.76 | A | ||
IHS(OC2) | High-side peak current limit TPSM64406 | Peak current limit on HS FET when Duty Cycle approaches 0% | 4.6 | 5.5 | 6.8 | A |
ILS(OC1) | Low-side valley current limit TPSM64404 | Valley current limit on LS FET | 3.2 | A | ||
ILS(OC2) | Low-side valley current limit TPSM64406 | Valley current limit on LS FET | 2.8 | 3.7 | 4.5 | A |
ILS2(NOC) | Low-side negative current limit TPSM64406 | Sinking current limit on LS FET | 2 | 2.8 | 3.6 | A |
ILPEAK1(min-0) | Minimum peak inductor current at minimum duty cycle TPSM64404 | VVCC = 3.3 V, tpulse ≤ 100 ns | 0.71 | A | ||
ILPEAK1(min-100) | Minimum peak inductor current at maximum duty cycle TPSM64404 | VVCC = 3.3 V, tpulse ≥ 1 µs | 0.19 | A | ||
ILPEAK2(min-0) | Minimum peak inductor current at minimum duty cycle TPSM64406 | VVCC = 3.3 V, tpulse ≤ 100 ns | 0.5 | 0.79 | 1.1 | A |
ILPEAK2(min-100) | Minimum peak inductor current at maximum duty cycle TPSM64406 | VVCC = 3.3 V, tpulse ≥ 1 µs | 0.25 | 0.3 | 0.35 | A |
VHiccup-FB | Hiccup threshold on FB pin - dual output mode, adjustable output option | HS FET On-time > 165 ns | 0.25 | 0.3 | 0.35 | V |
tHiccup-1 | Wait time before entering Hiccup - single and dual output mode | 126 | 128 | 130 | Curent Limit cycles | |
tHiccup-2 | Hiccup time before re-start | 50 | 88 | ms | ||
POWER GOOD | ||||||
VPGTH-1 | Power Good threshold (PG1/2) | PGOOD low, VVOSNS1/2 rising | 93% | 95% | 97% | |
VPGTH-2 | Power Good threshold (PG1/2) | PGOOD high, VVOSNS1/2 falling | 92% | 94% | 96% | |
VPGTH-3 | Power Good threshold (PG1/2) | PGOOD high, VVOSNS1/2 rising | 105% | 107% | 110% | |
VPGTH-4 | Power Good threshold (PG1/2) | PGOOD low, VVOSNS1/2 falling | 104% | 106% | 109% | |
tPGOOD(R) | PG1/2 delay from VVOSNS1/2 valid to PGOOD high during start-up | VVOSNS1/2 = 3.3 V | 1.5 | 2.1 | 3 | ms |
tPGOOD(F) | PG1/2 delay from VVOSNS1/2 invalid to PGOOD low | VVOSNS1/2 = 3.3 V | 25 | 40 | 70 | µs |
IPG(LKG) | PG1/2 pin leakage current when open drain output is high | VPG = 3.3 V | 0.075 | µA | ||
VPG-D(LOW) | PG pin output low-level voltage for both channels | IPG = 1 mA, VEN = 0 V. | 400 | mV | ||
RPG-1 | Pull down MOSFET resistance | IPG = 1 mA, VEN = 3.3 V. | 30 | 90 | Ω | |
VIN(PG_VALID) | Minimum VIN for valid PG output | Pull up resistance on PG - RPG = 10 kΩ, Voltage Pull up on PG - VPULLUP_PG= 3 V, VPG-D(LOW)= 0.4 V | 0.45 | 1.2 | V | |
THERMAL SHUTDOWN | ||||||
TJ(SD) | Thermal shutdown threshold (1) | Temperature rising | 160 | 170 | 180 | °C |
TJ(HYS) | Thermal shutdown hysteresis (1) | 10 | °C |