SLVSGJ4C october   2022  – july 2023 TPSM82912 , TPSM82913 , TPSM82913E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Smart Config (S-CONF)
      2. 7.3.2  Device Enable (EN/SYNC)
      3. 7.3.3  Device Synchronization (EN/SYNC)
      4. 7.3.4  Spread Spectrum Modulation
      5. 7.3.5  Output Discharge
      6. 7.3.6  Undervoltage Lockout (UVLO)
      7. 7.3.7  Power-Good Output
      8. 7.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 7.3.9  Current Limit and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency Pulse Width Modulation
      2. 7.4.2 Low Duty Cycle Operation
      3. 7.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 7.4.4 Second Stage L-C Filter Compensation (Optional)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 External Component Selection
          1. 8.2.2.2.1 Switching Frequency Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Setting the Output Voltage
          6. 8.2.2.2.6 NR/SS Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Layout Example

GUID-20220907-SS0I-CVRG-TVN0-N1BJR8NTWJH8-low.gif Figure 8-15 Recommended Layout for Single L-C Filter
Note: For a single L-C configuration, the feedback sense is placed near the VOUT capacitors. For a second L-C filter design, the feedback sense is placed near the load after the VOUT_FILT capacitors.
GUID-20220907-SS0I-NMB7-CBGQ-D9NWTF8F3HGF-low.gif Figure 8-16 Recommended Layout for Design with Second L-C Filter
Note: The ferrite bead can be placed closer to the device as long as it is placed > 8 mm from the device. This placement avoids capacitive and electromagnetic coupling to the output of the ferrite bead. If the ferrite bead is placed < 8 mm, the filtering effect of the ferrite bead is greatly reduced. If the ferrite bead is routed through a via to the back side of the board, ensure adequate ground plane between the layers if the ferrite bead is in this area.