SLVSGJ4C October   2022  – July 2023 TPSM82912 , TPSM82913 , TPSM82913E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Smart Config (S-CONF)
      2. 7.3.2  Device Enable (EN/SYNC)
      3. 7.3.3  Device Synchronization (EN/SYNC)
      4. 7.3.4  Spread Spectrum Modulation
      5. 7.3.5  Output Discharge
      6. 7.3.6  Undervoltage Lockout (UVLO)
      7. 7.3.7  Power-Good Output
      8. 7.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 7.3.9  Current Limit and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency Pulse Width Modulation
      2. 7.4.2 Low Duty Cycle Operation
      3. 7.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 7.4.4 Second Stage L-C Filter Compensation (Optional)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 External Component Selection
          1. 8.2.2.2.1 Switching Frequency Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Setting the Output Voltage
          6. 8.2.2.2.6 NR/SS Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Design Requirements

The external components have to fulfill the needs of the application, but also meet the stability criteria of the control loop of the device. The device is optimized to work within a range of external components, and can be optimized for the following:

  • Efficiency
  • Output ripple
  • Component count
  • Lowest noise

Typical applications that have input voltages of ≤ 6 V use a 2.2-MHz switching frequency. Applications that have input voltages > 6 V can be optimized for efficiency using a 1-MHz switching frequency. In this case, the output voltage ripple doubles, which is typically acceptable when powering high speed ADCs. Optimization for powering clock and PLL circuits that need a 3.3-V output use a 2.2-MHz switching frequency, minimizing output voltage ripple and low frequency noise.

For the application cases that are not found in Table 8-2, there are two methods to design the TPSM8291x circuit. Section 8.2.2.1 uses Webench to design the circuit automatically or the calculations in Section 8.2.2.2 can be used instead.

Table 8-2 Typical Single L-C Filter Design Recommendations
DESIGN GOALVINVOUTFSWOUTPUT CAPACITORS 3
Typical12 V(1)≤ 2.0 V(1)1 MHz3 × 22 µF, 10 V, 0805
Higher efficiency (with higher ripple and noise)12 V2.0 V < VOUT ≤ 3.3 V1 MHz3 × 22 µF, 10 V, 0805
Low ripple, noise PLL and Clock Supply12 V2.6 V ≤ VOUT ≤ 3.3 V2.2 MHz3 × 22 µF, 10 V, 0805
Typical12 V> 3.3 V2.2 MHz
Typical5 V≤ 3.3 V2.2 MHz3 × 22 µF, 10 V, 0805
Typical5 V> 3.3 V2.2 MHz1 × 47 µF, 1210 and 2 × 22 µF, 10 V, 0805
(1) The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This is especially important for input voltages above 12 V or output voltages below 1 V. See Section 8.2.2.2.1.
(2) For output capacitor part numbers, see Table 8-5.

The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20-μVRMS noise typically. A second stage filter is added to provide additional attenuation of the output voltage ripple. The output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to Table 8-3 for second stage L-C filter recommendations based on the output voltage.

Table 8-3 Second Stage L-C (Ferrite Bead) Filter Design Recommendations
VOUT (V)FERRITE BEAD IMPEDANCE (AT 100 MHZ)(2)OUTPUT CAPACITORS (1)
≤ 3.3 V8 Ω to 20 Ω2 × 22 µF, 10 V, 0805
> 3.3 V8 Ω to 20 Ω3 × 22 µF, 10 V, 0805
(1) For output capacitor part numbers, see Table 8-5.
(2) For second stage L-C filter part numbers, see Table 8-5.