SLUSF98 November 2024 TPSM84338
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 1 | A | Enable input to the converter. Driving EN high or leaving this pin floating enables the converter. An external resistor divider can be used to implement an adjustable VIN UVLO function. |
FB | 2 | A | Output feedback input. Connect FB to the tap of an external resistor divider from the output to GND to set output voltage. |
GND | 3 | G | Ground pin. Connected to the source of the low-side FET as well as the ground pin for the controller circuit. Connect to system ground and the ground side of CIN and COUT. The path to CIN must be as short as possible. |
VOUT | 4 | P | Output voltage. This pin is connected to the internal buck inductor. Connect the pin to the output load and connect external output capacitors between this pin and GND. |
SW | 5 | P | Switching node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI. |
VIN | 6 | P | Supply input pin to internal LDO and high-side FET. Input bypass capacitors must be directly connected to this pin and GND. |
MODE | 7 | A | Mode selection pin in light load condition and Power-Good / Soft-Start function. See Mode Selection for details. |
SS/PG | 8 | A | This pin can be a soft-start function or Power-Good function depending on the mode pin configuration. If the soft-start function is selected, an external capacitor connected from this pin to GND defines the rise time for the internal reference voltage. If Power-Good function is selected, this is an open drain power-good indicator, which is asserted low if output voltage is out of PG threshold, overvoltage, or if the device is under thermal shutdown, EN shutdown, or during soft start. |
RT/SYNC | 9 | A | Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. See Section 6.3.5 for details. |