7.3.3 Synchronization (CLK)

The TPSM84824 switching frequency can also be synchronized to an external clock from 200 kHz to 1.6 MHz. Not all V_IN, V_OUT, and I_OUT conditions can be set to all of the frequencies in this range due to on-time or off-time limitations. See Table 2 for the allowable operating ranges.

An internal Phase Locked Loop (PLL) has been implemented to allow synchronization and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin (pin 24) with a duty cycle from 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of the RT/CLK pin.

Before the external clock is present the device operates in RT mode and the switching frequency is set by the RT resistor, R_RT. Select R_RT to set the frequency close to the external synchronization frequency. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock.

During operation, if the external clock is removed, the internal clock frequency begins to drop. After 10 μs without receiving a clock pulse, the device returns to RT mode. Output undershoot can occur while the switching frequency drops and returns to the frequency set by the RT resistor.