The following list
summarizes the essential guidelines for PCB layout and component
placement to optimize DC/DC module performance, including thermals
and EMI signature.
- Use a four-layer PCB with two-ounce copper
thickness for good thermal performance and with maximum
ground plane.
- Place input
capacitors as close as possible to the VIN pins. Note the
dual and symmetrical arrangement of the input capacitors
based on the VIN1 and VIN2 pins located on each side of the
module package. The high-frequency currents are split in two
and effectively flow in opposing directions such that the
related magnetic fields contributions cancel each other,
leading to improved EMI performance.
- Use low-ESR 1206 or 1210 ceramic capacitors with
X7R or X7S dielectric.
- Make ground return paths for the input capacitors
consist of localized top-side planes that connect
to the PGND pads under the module.
- Make VIN traces as wide as possible to reduce
trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
Even though the VIN pins are connected internally,
use a wide polygon plane on a bottom PCB layer to
connect these pins together and to the input
supply.
- Place output capacitors as close as possible to the
VOUT pins. A similar dual and symmetrical arrangement of the
output capacitors enables magnetic field cancellation and
EMI mitigation.
- Make ground return paths for the output
capacitors consist of localized top-side planes
that connect to the PGND pads under the
module.
- Make VOUT traces as wide as possible to reduce
trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
Even though the VOUT pins are connected
internally, use a wide polygon plane on a bottom
PCB layer to connect these pins together and to
the load, thus reducing conduction loss and
thermal stress.
- Keep the FB trace
as short as possible by placing the feedback resistors close
to the FB pin. Reduce noise sensitivity of the output
voltage feedback path by placing the resistor divider close
to the FB pin, rather than close to the load. FB is the
input to the voltage-loop error amplifier and represents a
high-impedance node sensitive to noise. Route a trace from
the upper feedback resistor to the required point of output
voltage regulation. Place the voltage feedback loop away
from the high-voltage switching trace, and preferably has
ground shield.
- Provide enough
PCB area for proper heatsinking. Use sufficient copper area
to achieve a low thermal impedance commensurate with the
maximum load current and ambient temperature conditions. For
operation at full rated load, the top-side ground plane is
an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed pads (PGND) of the
package to the PCB ground plane. If the PCB has multiple
copper layers, connect these thermal vias to inner-layer
ground planes.