SLUSF73 Data sheet

SLUSF73 august 2023 TPSM8S6C24

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

MOY|45
- MPQF759

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.6.36 (43h) VOUT_UV_WARN_LIMIT

CMD Address	43h
Write Transaction:	Write Word
Read Transaction:	Read Word
Format:	ULINEAR16 Relative or Absolute per VOUT_MODE
Phased:	No
NVM Back-up:	EEPROM
Updates:	On-the-fly

The VOUT_UV_WARN_LIMIT command sets the value of the output voltage at the sense or output pins that causes an output voltage low warning. The VOUT_UV_WARN_LIMIT sets an undervoltage threshold relative to the current VOUT_COMMAND. Updates to VOUT_COMMAND do not update VOUT_UV_WARN_LIMIT when the absolute format is used.

When the sensed output voltage exceeds the VOUT_UV_WARN_LIMIT threshold, the following actions are taken:

Set the VOUT bit in the STATUS_WORD.
Set the VOUT_UVW bit in the STATUS_VOUT register.
Notify the host per PMBus 1.3.1 Part II specification, section 10.2.

Figure 8-42 (43h) VOUT_UV_WARN_LIMIT Register Map

15	14	13	12	11	10	9	8
RW	RW	RW	RW	RW	RW	RW	RW
VOUT_UVW (High Byte)

7	6	5	4	3	2	1	0
RW	RW	RW	RW	RW	RW	RW	RW
VOUT_UVW (Low Byte)

LEGEND: R/W = Read/Write; R = Read only

Table 8-53 Register Field Descriptions

Bit	Field	Access	Reset	Description
15:0	VOUT_ UVW	RW	NVM	Sets the undervoltage warning limit. Format is per VOUT_ MODE.

Hardware Mapping and Supported Values

The Hardware for VOUT_UV_WARN_LIMIT is implemented as a fixed percentage relative to the current output voltage target. Depending on the VOUT_MODE setting, the value written to VOUT_UV_WARN_LIMIT must be mapped to the hardware percentage.

Programmed values not exactly equal to one of the hardware relative values is rounded down to the next available relative value supported by hardware. The hardware supports values from 84% to 97% VOUT_COMMAND in 1% steps.

Attempts to write (43h) VOUT_UV_WARN_LIMIT to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.