SLUSF73 Data sheet | TI.com

SLUSF73 august 2023 TPSM8S6C24

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

MOY|45
- MPQF759

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.6.17 (1Bh) SMBALERT_MASK_MFR

CMD Address	1Bh (with CMD byte = 80h)
Write Transaction:	Write Word
Read Transaction:	Block-Write/Block-Read Process Call
Format:	Unsigned Binary (1 byte)
Phased:	No
NVM Back-up:	EEPROM
Updates:	On-the-fly

SMBALERT_MASK bits for STATUS_MFR

Figure 8-23 (1Bh) SMBALERT_MASK_MFR Register Map

7	6	5	4	3	2	1	0
RW	RW	R	R	RW	RW	RW	R
mPOR	mSELF	0	0	mRESET	mBCX	mSYNC	0

LEGEND: R/W = Read/Write; R = Read only

Table 8-30 Register Field Descriptions

Bit	Field	Access	Reset	Description
7	mPOR	RW	NVM	0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.
6	mSELF	RW	NVM	0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. Due to variations in AVIN UVLO, unmasking this bit can result in SMBALERT being asserted on power up.
5	Not supported	R	0b	Not supported
4	Not supported	R	0b	Not supported
3	mRESET	RW	NVM	0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.
2	mBCX	RW	NVM	0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.
1	mSYNC	RW	NVM	0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. When the Loop Controller device of a multi-phase stack is programmed for Auto Detect SYNC, unmasking this bit can result in a momentary assertion of SMBALERT when the multi-phase stack is enabled.
0	Not supported	R	0b	Not supported