SBOSA52B november   2022  – august 2023 TRF0206-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential Amplifier
      2. 7.3.2 Single-Supply Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving a High-Speed ADC
      2. 8.1.2 Calculating Output Voltage Swing
      3. 8.1.3 Thermal Considerations
    2. 8.2 Typical Application
      1. 8.2.1 TRF0206-SP Driving an AFE7950-SP Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Specifications correspond to the respectively identified subgroup temperature, unless otherwise noted. Test conditions at
TA = 25°C, VDD = 3.3 V, single-ended input with RS = 50 Ω, differential output with ZL = 100 Ω, unless otherwise noted.
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal 3-dB bandwidth Vo = 100 mVPP 6.5 GHz
LSBW Large-signal 3-dB bandwidth Vo = 1 VPP 6.5 GHz
Bandwidth for 1.5-dB flatness 4.8 GHz
S21 Power gain f = 2 GHz 12.5 dB
S11 Input return loss f = 10 MHz to 4 GHz -10 dB
S12 Reverse isolation f = 10 MHz to 4 GHz -35 dB
Gain imbalance f = 10 MHz to 5 GHz ±0.4 dB
Phase imbalance f = 10 MHz to 5 GHz ±3 °
CMRR Common-mode rejection ratio(2) f = 2 GHz -30 dB
HD2 Second-order harmonic distortion f = 0.5 GHz, Po = +2 dBm -65 dBc
f = 1 GHz, Po = +2 dBm -60
f = 2 GHz, Po = +2 dBm -60
f = 4 GHz, Po = +2 dBm -60
HD3 Third-order harmonic distortion f = 0.5 GHz, Po = +2 dBm -65 dBc
f = 1 GHz, Po = +2 dBm -65
f = 2 GHz, Po = +2 dBm -68
f = 4 GHz, Po = +2 dBm -58
OP1dB Output 1-dB compression point f = 0.5 GHz 8.5 dBm
f = 1 GHz 10
f = 2 GHz 12
f = 4 GHz 10.5
f = 6 GHz 10
OIP2 Output second-order intercept point f = 0.5 GHz, Po = –5 dBm per tone,
10 MHz spacing		 65 dBm
f = 1 GHz, Po = –5 dBm per tone,
10 MHz spacing		 62
f = 2 GHz, Po = –5 dBm per tone,
10 MHz spacing		 58
f = 4 GHz, Po = –5 dBm per tone,
10 MHz spacing		 55
f = 6 GHz, Po = –5 dBm per tone,
10 MHz spacing		 55
OIP3 Output third-order intercept point f = 0.5 GHz, Po = –5 dBm per tone,
10 MHz spacing		 32 dBm
f = 1 GHz, Po = –5 dBm per tone,
10 MHz spacing		 35
f = 2 GHz, Po = –5 dBm per tone,
10 MHz spacing		 38
f = 4 GHz, Po = –5 dBm per tone,
10 MHz spacing		 35
f = 6 GHz, Po = –5 dBm per tone,
10 MHz spacing		 32
NF Noise figure f = 0.5 GHz 7.5 dB
f = 1 GHz 7.5
f = 2 GHz 8
f = 4 GHz 9
f = 6 GHz 9
IMPEDANCE
ZO-DIFF Differential output impedance f = dc (internal to the device) 5 Ω
ZIN Single-ended input impedance With INM terminated with 50 Ω 50 Ω
TRANSIENT
VOMAX Output max operating voltage
(differential)		 1.7 VPP
VOSAT Output saturated voltage level (differential) f = 4 GHz 3.5 VPP
TREC Over-drive recovery time Using a 0.5-VP input pulse of 2-ns duration 0.35 ns
POWER SUPPLY
IQA Active current Current on VDD pin, PD = 0 [1, 2, 3] 85 130 170 mA
IQPD Power-down quiescent current Current on VDD pin, PD = 1 [1, 2, 3] 2 7 16 mA
ENABLE
VPDHIGH PD pin logic high 1.55 V
VPDLOW PD pin logic low 0.7 V
IPDBIAS PD bias current (current on PD pin) PD = high (1.8-V logic) 50 100 µA
PD = low (3.3-V logic) 200 300
CPD PD pin capacitance 3 pF
TON Turn-on time 50% VPD to 90% RF 200 ns
TOFF Turn-off time 50% VPD to 10% RF 100 ns
(1) For subgroup definitions, please see Quality Conformance Inspection.
(2) CMRR is calculated using the formula (S21-S31) / (S21+S31). Port-1: INP, Port-2: OUTP, Port-3: OUTM.