TRF372017 Integrated IQ Modulator PLL/VCO
- SLWS224E August 2010 – January 2016 TRF372017
  
  PRODUCTION DATA.

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DATA SHEET

TRF372017 Integrated IQ Modulator PLL/VCO

1 Features

Fully Integrated PLL/VCO and IQ Modulator
LO Frequency from 300 MHz to 4.8 GHz
76-dBc Single-Carrier WCDMA ACPR at –8-dBm Channel Power
OIP3 of 26 dBm
P1dB of 11.5 dBm
Integer/Fractional PLL
Phase Noise –132 dBc/Hz
(at 1 MHz, f_VCO of 2.3 GHz)
Low Noise Floor: –160 dBm/Hz
Input Reference Frequency Range: Up to
160 MHz
VCO Frequency Divided by 1-2-4-8 Output

2 Applications

Wireless Infrastructure
- CDMA: IS95, UMTS, CDMA2000, TD-SCDMA
- TDMA: GSM, IS-136, EDGE/UWC-136
- LTE
Wireless Local Loop
Point-to-Point Wireless Access
Wireless MAN Wideband Transceivers

3 Description

TRF372017 is a high-performance, direct up-conversion device, integrating a high-linearity, low-noise IQ modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide, continuous tuning range of 300 MHz to 4800 MHz. The LO is available as an output with independent frequency dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is controlled through a 3-wire serial programming interface (SPI). A control pin invokes power-save mode to reduce power consumption while keeping the VCO locked for fast start-up.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TRF372017	VQFN (48)	7.00 mm × 7.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

spacing

Block Diagram

4 Revision History

Changes from D Revision (September 2013) to E Revision

Added Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from C Revision (May 2012) to D Revision

Changed text string from Reg 1, B[30..28] = [000] to Reg 0, B[30..28] = [000] in the Description column associated with RB_REG<0>, RB_REG<1>, and RB_REG<2>Go

Changes from B Revision (March 2012) to C Revision

Added graph titles to Figure 56 and 57 that were missing in Revision B.Go

Changes from A Revision (August 2010) to B Revision

Deleted Comments column from Table 1Go
Changed Figures 12 through Figure 27Go
Changed the text under Integer and Fractional Mode Selection through Practical Limit on Maximum PFD Frequency.Go
Changed RDIV = 20 to RDIV = 2 in Setup Example for Fractional Mode.Go
Changed Recommended Value of EN_LD_ISOURCE from 1 to 0 in Table 1Go
Changed column heading from Default Value to Reset Value in register tables 1, 2, 3, 4, 5, 6, and 7Go
Added recommended programming [xx] to various Description statements in register tables 2, 5, 6, and 7.Go
Changed Register 4, Bit21/Bit22 Description statement from Off to Normal.Go
Changed Column heading from Default Value to Reset Value in Readback mode section, Register 0Go
Changed Bit5 name from CHIP_ID to CHIP_ID _0 and changed Bit6 name from NU to CHIP_ID_1, Reset Value to 1Go
Changed image in Figure 87. Go
Changed the text in the Application Layout, and added link to Figure 95Go

5 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
BBI_P	27	I	Base-band in-phase input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_N is required.
BBI_N	28	I	Base-band in-phase input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_P is required.
BBQ_N	9	I	Base-band in-quadrature input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_P is required.
BBQ_P	10	I	Base-band in-quadrature input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_N is required.
CLK	47	I	SPI clock input. Digital input. High impedance.
CP_OUT	40	O	Charge pump output
DATA	46	I	SPI data input. Digital input. High impedance.
EXT_VCO	36	I	External local oscillator input. High impedance. Normally AC-coupled.
GND	6, 8, 11, 12, 13, 15, 16, 17, 19, 22, 23, 24, 25, 26, 29, 31, 37, 39, 42, 44	—	Ground
GND_DIG	4	—	Digital ground
LD	5	O	PLL lock detect output, as configured by MUX_CTRL. Digital output pins can source or sink up to 8 mA of current.
LE	45	I	SPI latch enable. Digital input. High impedance.
LO_OUT_N	33	O	Local oscillator output: negative terminal. Open collector output. A pullup is required. Normally AC-coupled.
LO_OUT_P	34	O	Local oscillator output: positive terminal. Open collector output. A pullup is required. Normally AC-coupled.
PS	1	I	Power saving mode enable (Low = normal mode; High = power saving mode)
RDBK	2	O	SPI internal registers readback output. Digital output pins can source or sink up to 8 mA of current.
REFIN	43	I	Reference clock input. High impedance. Normally AC-coupled.
RFOUT	18	O	RF output. Internally matched to 50-Ω output. Normally AC-coupled.
RSVD	14	—	Reserved. Normally open.
SCAN_EN	48	I	Internal testing mode digital input. Connect to ground in normal operation
VCC_D2S	20	—	5-V modulator output buffer power supply
VCC_DIG	3	—	3.3-V digital power supply
VCC_LO1	7	—	3.3-V Tx path local oscillator chain power supply
VCC_LO2	30	—	3.3-V output local oscillator chain power supply
VCC_MIX	21	—	5-V modulator power supply
VCC_PLL	41	—	3.3-V PLL power supply
VCC_VCO1	35	—	3.3-V VCO power supply
VCC_VCO2	32	—	3.3-V to 5-V VCO power supply
VTUNE	38	I	VCO control voltage input

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽³⁾

		MIN	MAX	UNIT
	Supply voltage⁽²⁾	–0.3	5.5	V
	Digital I/O voltage	–0.3	V_CC + 0.5	V
T_J	Operating virtual junction temperature	–40	150	°C
T_A	Operating ambient temperature	–40	85	°C
T_stg	Storage temperature	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) ESD rating not valid for RF sensitive pins.

6.2 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC5V	5-V power supply voltage	4.5	5	5.5	V
V_CC3V	3.3-V power supply voltage	3	3.3	3.6	V
VCC_VCO2	3.3-V to 5-V power supply voltage	3	3.3	5.5	V
T_A	Operating ambient temperature	–40		85	°C
T_J	Operating virtual junction temperature	–40		125	°C

6.3 Thermal Information

THERMAL METRIC⁽¹⁾		TRF372017	UNIT
		RGZ (VQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	30.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.0	°C/W
R_θJB	Junction-to-board thermal resistance	8.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	7.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Electrical Characteristics

V_CC5V = 5 V, V_CC3V = 3.3 V, VCC_VCO2 = 3.3 V, T_A = 25°C, internal LO, internal VCM (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC PARAMETERS
I_CC	Total supply current, LO on⁽¹⁾	3.3-V power supply, LO on		200	250	mA
I_CC	Total supply current, LO on⁽¹⁾	5-V power supply, LO on		117	148	mA
	Supply current, LO on⁽¹⁾	VCC_DIG, LO on		3	5	mA
		VCC_LO1 and VCC_LO2		121	130	mA
		VCC_D2S		43	60	mA
		VCC_MIX		74	90	mA
		VCC_VCO1		20	28	mA
		VCC_VCO2		17	20	mA
		LO_OUT_N and LO_OUT_P		17	28	mA
		VCC_PLL		24	40	mA
	Total supply current, LO off⁽¹⁾	3.3-V power supply, LO off		165	204	mA
	Total supply current, LO off⁽¹⁾	5-V power supply, LO off		117	149	mA
	Total supply current, PS on⁽¹⁾	3.3-V power supply, PS on		65	94	mA
	Total supply current, PS on⁽¹⁾	5-V power supply, PS on		51	73	mA
BASEBAND INPUTS
V_cm	I and Q input DC common voltage⁽²⁾	Externally generated		1.7		V
V_cm	I and Q input DC common voltage⁽²⁾	Set internally	1.6	1.7	1.85	V
BW	1-dB input frequency bandwidth			1000		MHz
Z_I	Input Impedance	Resistance		5		kΩ
Z_I	Input Impedance	Parallel Capacitance		3		pF
BASEBAND INPUT DC OFFSET CONTROL D/A⁽³⁾
	Number of bits	Programmed through SPI		8
	Programmable DC offset setting	\|BBI_P - BBI_N\| or \|BBQ_P - BBQ_N\|, 100-Ω differential load			0.02	V
DIGITAL INTERFACE
V_IH	High-level input voltage		2	3.3		V
V_IL	Low-level input voltage		0		0.8	V
V_OH	High-level output voltage	Referenced to VCC_DIG	0.8 × Vcc			V
V_OL	Low-level output voltage	Referenced to VCC_DIG			0.2 × Vcc	V
REFERENCE OSCILLATOR PARAMETERS
F_ref	Reference frequency				160	MHz
	Reference input sensitivity		0.2		3.3	Vp-p
	Reference input impedance	Parallel capacitance		5		pF
	Reference input impedance	Parallel resistance	3900			Ω
PFD CHARGE PUMP
	PFD frequency⁽⁴⁾				100	MHz
I_CP	Charge pump current	SPI programmable		1.94		mA
IQ MODULATOR OUTPUT, F_LO = 750 MHz
G	Voltage gain	Output RMS voltage over se input I (or Q) RMS voltage	–4	–3.2	–2.4	dB
P1dB	Output compression point			11		dBm
IP3	Output IP3	2 input tones at 4.5 and 5.5 MHz		26		dBm
IP2	Output IP2	2 input tones at 4.5 and 5.5 MHz		56.5		dBm
	Carrier feedthrough	Unadjusted		–43.5		dBm
	Sideband suppression	Unadjusted		–46		dBc
	Output return loss			10		dB
	Output noise	DC only to BB inputs; 13-MHz offset from LO; P_out = –10 dBm		–162		dBm/Hz
IQ MODULATOR OUTPUT, F_LO = 900 MHz
G	Voltage gain	Output RMS voltage over se input I (or Q) RMS voltage	–4	–3.4	–2.4	dB
P1dB	Output compression point			11		dBm
IP3	Output IP3	2 input tones at 4.5 and 5.5 MHz		26.5		dBm
IP2	Output IP2	2 input tones at 4.5 and 5.5 MHz		56.5		dBm
	Carrier feedthrough	Unadjusted		–43		dBm
	Sideband suppression	Unadjusted		–45		dBc
	Output return loss			10		dB
	Output noise	DC only to BB inputs; 13-MHz offset from LO; P_out= –10 dBm		–160		dBm/Hz
IQ MODULATOR OUTPUT, F_LO = 2150 MHz
G	Voltage gain	Output RMS voltage over se input I (or Q) RMS voltage	–4.2	–3.1	–2	dB
P1dB	Output compression point			11.5		dBm
IP3	Output IP3	2 input tones at 4.5 and 5.5 MHz		25		dBm
IP2	Output IP2	2 input tones at 4.5 and 5.5 MHz		56		dBm
	Carrier feedthrough	Unadjusted		–40		dBm
	Sideband suppression	Unadjusted		–32		dBc
	Output return loss			10		dB
	Output noise	DC only to BB inputs; 13-MHz offset from LO; P_out = –10 dBm		–158		dBm/Hz
ACPR	Adjacent-channel power ratio	1 WCDMA signal; P_out = –8 dBm		–75		dBc
ACPR	Adjacent-channel power ratio	2 WCDMA signals; P_out = –11 dBm per carrier		71		dBc
IQ MODULATOR OUTPUT, F_LO = 2700 MHz
G	Voltage gain	Output RMS voltage over se input I (or Q) RMS voltage	–4.1	–2.7	–1.3	dB
P1dB	Output compression point			12		dBm
IP3	Output IP3	2 input tones at 4.5 and 5.5 MHz		26.5		dBm
IP2	Output IP2	2 input tones at 4.5 and 5.5 MHz		50		dBm
	Carrier feedthrough	Unadjusted		–43		dBm
	Sideband suppression	Unadjusted		–41		dBc
	Output return loss			10		dB
	Output noise	DC only to BB inputs; 13-MHz offset from LO; P_out = –10 dBm		–153		dBm/Hz
LOCAL OSCILLATOR
F_VCO	Frequency range	VCO range	2400		4800	MHz
		Divide by 2	1200		2400
		Divide by 4	600		1200
		Divide by 8	300		600
	Free running VCO	10 kHz		–85		dBc/Hz
	Phase noise, Fout = 2.3 GHz	1 MHz		–132		dBc/Hz
		10 MHz		–150		dBc/Hz
		50 MHz		–153		dBc/Hz
P_LO	LO output power⁽⁵⁾	100-Ω differential, external load; single-ended	–2.5	3		dBm

(1) Maximum current is worst-case overvoltage, temperature, and expected process variations.

(2) The TRF372017 can generate the input common voltage internally or can accept an external common mode voltage. The two modes are selectable through SPI.

(3) When the internal input common mode voltage is selected, it is possible to apply some DC offset with the integrated D/A.

(4) See Application Information for discussion on selection of PFD frequency.

(5) With VCO frequency at 4.6 GHz and LO in divide-by-2 mode at 2.3 GHz

6.5 Timing Requirements - SPI: Writing Phase⁽¹⁾

		MIN	UNIT
t_h	Hold time, data to clock	20	ns
t_SU1	Setup time, data to clock	20	ns
T_(CH)	Clock low duration	20	ns
T_(CL)	Clock high duration	20	ns
t_SU2	Setup time, clock to enable	20	ns
t_(CLK)	Clock period	50	ns
t_W	Enable time	50	ns
t_SU3	Setup time, latch to data	70	ns

(1) See Figure 1 for timing diagram.

6.6 Timing Requirements - SPI: Read-Back Phase⁽¹⁾

		MIN	UNIT
t_h	Hold time, data to clock	20	ns
t_SU1	Setup time, data to clock	20	ns
T_(CH)	Clock low duration	20	ns
T_(CL)	Clock High duration	20	ns
t_SU2	Setup time, clock to enable	20	ns
t_d	Delay time, clock to readback data output	10	ns
t_W	Enable time⁽²⁾	50	ns
t_(CLK)	Clock period	50	ns

(1) See Figure 2 for timing diagram.

(2) Equals Clock period

Figure 1. SPI Write Timing Diagram

Figure 2. SPI Read-Back Timing Diagram

6.7 Typical Characteristics

V_CM = 1.7 V (internal), V_inBB = 300 mVrms single-ended sine wave in quadrature, V_CC3V = 3.3 V, V_CC5V = 5 V, f_BB = 4.5 MHz and 5.5 MHz, internal LO, T_A = 25°C; F_PFD = 1.6 MHz (unless otherwise noted).

Figure 3. Open-Loop Phase Noise
vs Frequency and Temperature

Figure 5. Open Loop Phase Noise
vs Frequency and Temperature

Figure 7. Open Loop Phase Noise
vs Frequency and Supply Voltage

Figure 9. Open Loop Phase Noise
vs Frequency and Supply Voltage

Figure 11. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 13. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 15. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 17. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 19. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 21. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 23. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 25. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 27. Noise at 13-MHz Offset
vs Frequency and Temperature With Internal VCO

Figure 29. Noise at 13-MHz Offset
vs Frequency and Temperature With External VCO

Figure 31. Noise at 13-MHz Offset
vs Output Power and Frequency

Figure 33. Voltage Gain
vs Frequency and Temperature at 750 MHz

Figure 35. Voltage Gain
vs Frequency and Temperature at 1500 MHz

Figure 37. Voltage Gain
vs Frequency and Temperature at 2650 MHz

Figure 39. Voltage Gain
vs Baseband Voltage Amplitude and Frequency

Figure 41. P1dB vs Frequency and Temperature

Figure 43. P1dB vs Frequency and Temperature at 900 MHz

Figure 45. P1dB vs Frequency and Temperature at 2150 MHz

Figure 47. P1dB vs Common-Mode Voltage and Frequency

Figure 49. OIP3 vs Frequency and Temperature

Figure 51. OIP3 vs Frequency and Temperature at 1030 MHz

Figure 53. OIP3 vs Frequency and Temperature at 2300 MHz

Figure 55. OIP3 vs Common-Mode Voltage and Frequency

Figure 57. OIP2 vs Frequency and Temperature

Figure 59. OIP2 vs Frequency and Temperature at 900 MHz

Figure 61. OIP2 vs Frequency and Temperature at 2150 MHz

Figure 63. Unadjusted Sideband Suppression
vs Frequency and Temperature

Figure 65. Unadjusted Sideband Suppression
vs Frequency and Temperature at 1030 MHz

Figure 67. Unadjusted Sideband Suppression
vs Frequency and Temperature at 2300 MHz

Figure 69. Unadjusted Sideband Suppression
vs Common-Mode Voltage and Frequency

Figure 71. Unadjusted Carrier Suppression
vs Frequency and Temperature at 900 MHz

Figure 73. Unadjusted Carrier Suppression
vs Frequency and Temperature at 1650 MHz

Figure 75. Unadjusted Carrier Suppression
vs Frequency and Temperature at 2850 MHz

Figure 77. Common-Mode Voltage
vs VREF_SEL Setting and Temperature

Figure 4. Open Loop Phase Noise
vs Frequency and Temperature

Figure 6. Open Loop Phase Noise
vs Frequency and Temperature

Figure 8. Open Loop Phase Noise
vs Frequency and Supply Voltage

Figure 10. Open Loop Phase Noise
vs Frequency and Supply Voltage

Figure 12. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 14. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 16. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 18. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 20. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 22. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 24. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 26. Closed Loop Phase Noise
vs Frequency and Temperature

Figure 28. Noise at 13-MHz Offset
vs Frequency and Supply Voltage With Internal VCO

Figure 30. Noise at 13-MHz Offset
vs Frequency and Supply Voltage With External VCO

Figure 32. Voltage Gain vs Frequency and Temperature

Figure 34. Voltage Gain
vs Frequency and Temperature at 900 MHz

Figure 36. Voltage Gain
vs Frequency and Temperature at 2150 MHz

Figure 38. Voltage Gain
vs Common-Mode Voltage and Frequency

Figure 40. Voltage Gain vs Frequency and Supply Voltage

Figure 42. P1dB vs Frequency and Temperature at 750 MHz

Figure 44. P1dB vs Frequency and Temperature at 1500 MHz

Figure 46. P1dB vs Frequency and Temperature at 2700 MHz

Figure 48. P1dB vs Frequency and Supply Voltage

Figure 50. OIP3 vs Temperature and Frequency at 900 MHz

Figure 52. OIP3 vs Frequency and Temperature at 1650 MHz

Figure 54. OIP3 vs Frequency and Temperature at 2850 MHz

Figure 56. OIP3 vs Baseband Voltage Amplitude and Frequency

Figure 58. OIP2 vs Frequency and Temperature at 750 MHz

Figure 60. OIP2 vs Frequency and Temperature at 1500 MHz

Figure 62. OIP2 vs Frequency and Temperature at 2650 MHz

Figure 64. Unadjusted Sideband Suppression
vs Frequency and Temperature at 900 MHz

Figure 66. Unadjusted Sideband Suppression
vs Frequency and Temperature at 1650 MHz

Figure 68. Unadjusted Sideband Suppression
vs Frequency and Temperature at 2850 MHz

Figure 70. Unadjusted Carrier Suppression
vs Frequency and Temperature

Figure 72. Unadjusted Carrier Suppression
vs Frequency and Temperature at 1030 MHz

Figure 74. Unadjusted Carrier Suppression
vs Frequency and Temperature at 2300 MHz

Figure 76. Unadjusted Carrier Suppression
vs Common-Mode Voltage and Frequency

Figure 78. Baseband Voltage Offset
vs IOFF Setting and Temperature