SLLS822C July   2007  – December 2024 TRSF3221E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings, IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Resistance Characteristics
    6. 5.6  Electrical Characteristics
    7. 5.7  Electrical Characteristics, Driver
    8. 5.8  Switching Characteristics, Driver
    9. 5.9  Electrical Characteristics, Receiver
    10. 5.10 Switching Characteristics, Receiver
    11. 5.11 Electrical Characteristics, Auto-Powerdown
    12. 5.12 Switching Characteristics, Auto-Powerdown
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
      2. 8.1.2 Application Performance Plot
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 ESD Ratings, IEC Specifications

PIN NAMETEST CONDITIONSVALUEUNIT
RIN, DOUT(2)HBM±15,000V
IEC 61000-4-2 Contact Discharge(1)(2)±8,000
IEC 61000-4-2 Air-Gap Discharge(1)(2)±15,000
(1) For the RGT and PW package only, a minimum of 1µF capacitor is required between VCC and GND to meet the specified IEC-ESD level.
(2) For optimized IEC ESD performance for DYY package, the recommendation is to have series resistor (≥ 50Ω), on all logic inputs directly connected to power or ground, to minimize the transient currents going into or out of the logic pins.