SCDS364E June   2015  – October 2019 TS5A22362

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for 2.5-V Supply
    6. 6.6 Electrical Characteristics for 3.3-V Supply
    7. 6.7 Electrical Characteristics for 5-V Supply
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Negative Signaling Capacity
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics for 2.5-V Supply

VCC = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT
Analog Switch
VCOM,
VNO, VNC 		Analog signal
range		 VCC – 5.5 VCC V
Ron ON-state
resistance		 VNC or VNO = VCC, 1.5 V,
VCC – 5.5 V
ICOM = –100 mA,		 COM to NO or NC,
see Figure 13 		25°C 2.7 V 0.65 0.94 Ω
Full 1.3
ΔRon ON-state
resistance match
between channels		 VNC or VNO = 1.5 V,
ICOM = –100 mA,		 COM to NO or NC,
see Figure 13 		25°C 2.7 V 0.023 0.11 Ω
Full 0.15
Ron(flat) ON-state
resistance
flatness		 VNC or VNO = VCC, 1.5 V,
VCC – 5.5 V
ICOM = –100 mA,		 COM to NO or NC,
see Figure 13 		25°C 2.7 V 0.18 0.46 Ω
Full 0.5
INC(OFF),
INO(OFF) 		NC, NO
OFF leakage
current
VNC = 2.25 V, VCC – 5.5 V
VCOM = VCC – 5.5 V, 2.25 V
VNO = Open
COM to NO
or
VNO = 2.25 V, VCC – 5.5 V,
VCOM = VCC – 5.5 V, 2.25 V
VNC = Open
COM to NC		 See Figure 14 25°C 2.7 –50 50 nA
Full –375 375
ICOM(ON) COM
ON leakage
current		 VNC and VNO = Floating,
VCOM = VCC,VCC – 5.5 V		 See Figure 15 25°C 2.7 V –50 50 nA
Full –375 375
Digital Control Inputs (IN) (2)
VIH Input logic high Full 1.4 5.5 V
VIL Input logic low 0.6
IIH, IIL Input leakage current VIN = VCC or 0 25°C 2.7 V –250 250 nA
Full –250 250
Dynamic
tON Turnon time VCOM = VCC,
RL = 300 Ω,		 CL = 35 pF,
see Figure 17 		25°C 2.5 V 44 80 ns
Full 2.3 V to 2.7 V 120
tOFF Turnoff time VCOM = VCC,
RL = 300 Ω,		 CL = 35 pF,
see Figure 17 		25°C 2.5 V 22 70 ns
Full 2.3 V to 2.7 V 70
tBBM Break-before-make time See Figure 18 25°C 2.5 V 1 7 ns
QC Charge injection VGEN = 0,
RGEN = 0,		 CL = 1 nF,
see Figure 22 		25°C 2.5 V 150 pC
CNC(OFF),
CNO(OFF) 		NC, NO
OFF capacitance		 VNC or VNO = VCC or GND, See Figure 16 25°C 2.5 V 70 pF
CCOM(ON) NC, NO, COM
ON capacitance		 VCOM = VCC or GND,
Switch ON, f = 10 MHz		 See Figure 16 25°C 2.5 V 370 pF
CI Digital input capacitance VI = VCC or GND See Figure 16 25°C 2.5 V 2.6 pF
BW Bandwidth RL = 50 Ω, –3 dB See Figure 18 25°C 2.5 V 17 MHz
OISO OFF isolation RL = 50 Ω f = 100 kHz,
see Figure 20 		25°C 2.5 V –66 dB
XTALK Crosstalk RL = 50 Ω f = 100 kHz,
see Figure 21 		25°C 2.5 V –75 dB
THD Total harmonic distortion RL = 600 Ω,
CL = 35 pF 		f = 20 Hz to
20 kHz,
see Figure 23 		25°C 2.5 V 0.01%
Supply
ICC Positive
supply current		 VCOM and VIN = VCC or GND,
VNC and VNO = Floating 		25°C 2.7 V 0.2 1.1 μA
Full 1.3
ICC Positive
supply current		 VCOM = VCC – 5.5 V,
VIN = VCC or GND,
VNC and VNO = Floating		 Full 2.7 V 3.3 μA
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.