SCDS361 Data sheet

SCDS361A October 2014 – July 2016 TS5A22364-Q1

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DGS|10
- MPDS035C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾ ⁽²⁾

			MIN	MAX	UNIT
V_CC	Supply voltage⁽³⁾		–0.5	6	V
V_NC	Analog voltage on NC1-NC2 pin⁽³⁾ ⁽⁴⁾ ⁽⁵⁾		V_CC – 6	V_CC + 0.5	V
V_NO	Analog voltage on NO1-NO2 pin⁽³⁾ ⁽⁴⁾ ⁽⁵⁾
V_COM	Analog voltage on COM1-COM2 pin⁽³⁾ ⁽⁴⁾ ⁽⁵⁾
I_I/OK	Analog port diode input clamp current	V_NC, V_NO, V_COM < 0 or V_NC, V_NO, V_COM > V_CC	–50	50	mA
I_NC I_NO I_COM	On-state switch continuous current	V_NC, V_NO, V_COM = 0 to V_CC	–150	150	mA
I_NC I_NO I_COM	On-state switch peak current⁽⁶⁾	V_NC, V_NO, V_COM = 0 to V_CC	–300	300	mA
I_RSH	Off-state switch shunt resistor current		–20	20	mA
V_IN	Digital input voltage		–0.5	6.5	V
I_IK	Digital input clamp current⁽³⁾ ⁽⁴⁾	V_IN < 0	–50	50	mA
I_CC I_GND	Continuous current through V_CC or GND		–100	100	mA
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(5) This value is limited to 5.5 V maximum.

(6) Pulse at 1-ms duration <10% duty cycle.

6.2 ESD Ratings

				MIN	MAX	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		–2500	2500	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011	all pins	–1500	1500	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_CC	Supply voltage	2.3	5.5	V
V_NC	Signal path voltage	V_CC – 5.5	V_CC	V
V_NO
V_COM
V_IN	Digital control	GND	V_CC	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾ ⁽²⁾		TS5A22364-Q1	UNIT
		DGS (VSSOP)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	163.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	56.4	°C/W
R_θJB	Junction-to-board thermal resistance	83.1	°C/W
ψ_JT	Junction-to-top characterization parameter	6.8	°C/W
ψ_JB	Junction-to-board characterization parameter	81.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.5 Electrical Characteristics—2.5-V Supply

V_CC = 2.3 V to 2.7 V, T_A = –40°C to +125°C (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS		T_A	V_CC	MIN	TYP	MAX	UNIT
ANALOG SWITCH
Analog signal	V_COM V_NO V_NC					V_CC – 5.5		V_CC	V
On-state resistance	R_on	V_NC or V_NO = V_CC, 1.5 V, V_CC – 5.5 V I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	2.7 V		0.65	0.94	Ω
On-state resistance	R_on	V_NC or V_NO = V_CC, 1.5 V, V_CC – 5.5 V I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	2.7 V			1.3	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	2.7 V		0.023	0.11	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	2.7 V			0.15	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO = V_CC, 1.5 V, V_CC – 5.5 V I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	2.7 V		0.18	0.46	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO = V_CC, 1.5 V, V_CC – 5.5 V I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	2.7 V			0.56	Ω
Shunt switch resistance	R_SH	I_NO or I_NC = 10 mA		–40°C to +125°C	2.7 V		25	55	Ω
On-state leakage current	I_COM(ON)	V_NC and V_NO = floating, V_COM = V_CC , V_CC – 5.5 V	See Figure 16	25°C	2.7 V	–200		200	nA
On-state leakage current	I_COM(ON)	V_NC and V_NO = floating, V_COM = V_CC , V_CC – 5.5 V	See Figure 16	–40°C to +125°C	2.7 V	–2500		2500	nA
DIGITAL CONTROL INPUTS (IN)⁽²⁾
Input logic high	V_IH			–40°C to +125°C		1.4		V_CC	V
Input logic low	V_IL			–40°C to +125°C				0.4	V
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		25°C	2.7 V	–250		250	nA
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		–40°C to +125°C	2.7 V	–250		250	nA
DYNAMIC
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	2.5 V		44	80	ns
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	2.3 V to 2.7 V			120	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	2.5 V		22	70	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	2.3 V to 2.7 V			70	ns
Break-before-make time	t_BBM		See Figure 19	25°C	2.5 V	1	7		ns
Charge injection	Q_C	V_GEN = 0, R_GEN = 0,	C_L = 1 nF, See Figure 23	25°C	2.5 V		215		pC
On-State NC, NO, COM capacitance	C_COM(ON)	V_COM= V_CC or GND, Switch ON, f = 10 MHz	See Figure 17	25°C	2.5 V		370		pF
Digital input capacitance	C_I	V_IN = V_CC or GND	See Figure 17	25°C	2.5 V		2.6		pF
Bandwidth	BW	R_L = 50 Ω, –3 dB	See Figure 20	25°C	2.5 V		17		MHz
Off-state isolation	O_ISO	R_L = 50 Ω	f = 100 kHz, See Figure 21	25°C	2.5 V		–66		dB
Crosstalk	X_TALK	R_L = 50 Ω	f = 100 kHz, See Figure 22	25°C	2.5 V		–75		dB
Total harmonic distortion	THD	R_L = 600 Ω, C_L = 35 pF	f = 20 Hz to 20 kHz, See Figure 24	25°C	2.5 V		0.01		%
SUPPLY
Positive supply current	I_CC	V_COM and V_IN = V_CC or GND, V_NC and V_NO = floating		25°C	2.7 V		0.2	1.1	μA
		V_COM and V_IN = V_CC or GND, V_NC and V_NO = floating		–40°C to +125°C	2.7 V			1.3	μA
		V_COM = V_CC – 5.5 V, V_IN = V_CC or GND, V_NC and V_NO = floating		–40°C to +125°C	2.7 V			3.3	μA

(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(2) All unused digital inputs of the device must be held at V_CC or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report, SCBA004.

6.6 Electrical Characteristics—3.3-V Supply

V_CC = 3 V to 3.6 V, T_A = –40°C to +125°C (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS		T_A	V_CC	MIN	TYP	MAX	UNIT
ANALOG SWITCH
Analog signal	V_COM V_NO V_NC					V_CC – 5.5		V_CC	V
On-state resistance	R_on	V_NC or V_NO ≤ V_CC, 1.5 V, V_CC – 5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	3 V		0.61	0.87	Ω
On-state resistance	R_on	V_NC or V_NO ≤ V_CC, 1.5 V, V_CC – 5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	3 V			0.97	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	3 V		0.024	0.13	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	3 V			0.13	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO ≤ V_CC, 1.5 V, V_CC – 5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	3 V		0.12	0.46	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO ≤ V_CC, 1.5 V, V_CC – 5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	3 V			0.5	Ω
Shunt switch resistance	R_SH	I_NO or I_NC = 10 mA		–40°C to +125°C	3 V		25	40	Ω
On-state leakage current	I_COM(ON)	V_NC and V_NO = floating, V_COM = V_CC,V_CC – 5.5 V	COM to NO or NC, See Figure 16	25°C	3.6 V	–200		200	nA
On-state leakage current	I_COM(ON)	V_NC and V_NO = floating, V_COM = V_CC,V_CC – 5.5 V	COM to NO or NC, See Figure 16	–40°C to +125°C	3.6 V	–2500		2500	nA
DIGITAL CONTROL INPUTS (IN)⁽²⁾
Input logic high	V_IH			–40°C to +125°C		1.4		V_CC	V
Input logic low	V_IL			–40°C to +125°C				0.6	V
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		25°C	3.6 V	–250		250	nA
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		–40°C to +125°C	3.6 V	–250		250	nA
DYNAMIC
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	3.3 V		34	80	ns
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	3 V to 3.6 V			80	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	3.3 V		19	70	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	3 V to 3.6 V			70	ns
Break-before-make time	t_BBM		See Figure 19	25°C	3.3 V	1	7		ns
Charge injection	Q_C	V_GEN = 0, R_GEN = 0,	C_L = 1 nF, See Figure 23	25°C	3.3 V		300		pC
On-State NC, NO, COM capacitance	C_COM(ON)	V_COM= V_CC or GND, f = 10 MHz	See Figure 17	25°C	3.3 V		370		pF
Digital input capacitance	C_I	V_IN = V_CC or GND	See Figure 17	25°C	3.3 V		2.6		pF
Bandwidth	BW	R_L = 50 Ω, –3 dB	Switch ON, See Figure 20	25°C	3.3 V		17.5		MHz
Off-state isolation	O_ISO	R_L = 50 Ω	f = 100 kHz, See Figure 21	25°C	3.3 V		–68		dB
Crosstalk	X_TALK	R_L = 50 Ω	f = 100 kHz, See Figure 22	25°C	3.3 V		–76		dB
Total harmonic distortion	THD	R_L = 600 Ω, C_L = 35 pF	f = 20 Hz to 20 kHz, See Figure 24	25°C	3.3 V		0.008		%
SUPPLY
Positive supply current	I_CC	V_COM and V_IN = V_CC or GND, V_NC and V_NO = floating		25°C	3.6 V		0.1	1.2	μA
		V_COM and V_IN = V_CC or GND, V_NC and V_NO = floating		–40°C to +125°C	3.6 V			1.3	μA
		V_COM = V_CC – 5.5 V, V_IN = V_CC or GND, V_NC and V_NO = floating		–40°C to +125°C	3.6 V			3.4	μA

(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(2) All unused digital inputs of the device must be held at V_CC or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report, SCBA004.

6.7 Electrical Characteristics—5-V Supply⁽¹⁾

V_CC = 4.5 V to 5.5 V, T_A = –40°C to +125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		T_A	V_CC	MIN	TYP	MAX	UNIT
ANALOG SWITCH
Analog signal	V_COM, V_NO, V_NC					V_CC – 5.5		V_CC	V
On-state resistance	R_on	V_NC or V_NO = V_CC, 1.6 V, V_CC = –5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	4.5 V		0.52	0.74	Ω
On-state resistance	R_on	V_NC or V_NO = V_CC, 1.6 V, V_CC = –5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	4.5 V			0.83	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.6 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	4.5 V		0.04	0.23	Ω
On-state resistance match between channels	ΔR_on	V_NC or V_NO = 1.6 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	4.5 V			0.30	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO = V_CC, 1.6 V, V_CC = –5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	25°C	4.5 V		0.076	0.46	Ω
On-state resistance flatness	R_on(flat)	V_NC or V_NO = V_CC, 1.6 V, V_CC = –5.5 V, I_COM = –100 mA	COM to NO or NC, See Figure 14	–40°C to +125°C	4.5 V			0.5	Ω
Shunt switch resistance	R_SH	I_NO or I_NC = 10 mA		–40°C to +125°C	4.5 V		16	36	Ω
On-state leakage current	I_COM(ON)	V_NC and V_NO = Floating, V_COM = VCC, V_CC – 5.5 V	See Figure 16	25°C	5.5 V	–200		200	nA
On-state leakage current	I_COM(ON)	V_NC and V_NO = Floating, V_COM = VCC, V_CC – 5.5 V	See Figure 16	–40°C to +125°C	5.5 V	–2500		2500	nA
DIGITAL CONTROL INPUTS (IN)⁽²⁾
Input logic high	V_IH			–40°C to +125°C		2.4		V_CC	V
Input logic low	V_IL			–40°C to +125°C				0.8	V
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		25°C	5.5 V	–250		250	nA
Input leakage current	I_IH, I_IL	V_IN = V_CC or 0		–40°C to +125°C	5.5 V	–250		250	nA
DYNAMIC
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	5 V		27	80	ns
Turnon time	t_ON	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	4.5 V to 5.5 V			80	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	25°C	5 V		13	70	ns
Turnoff time	t_OFF	V_COM = V_CC, R_L = 300 Ω	C_L = 35 pF, See Figure 18	–40°C to +125°C	4.5 V to 5.5 V			70	ns
Break-before-make time	t_BBM	V_NC = V_NO = V_CC/2 R_L = 300 Ω	C = 35 pF, See Figure 19	25°C	5 V	1	3.5		ns
Charge injection	Q_C	V_GEN = 0, R_GEN = 0	C_L = 1_L nF, See Figure 23	25°C	5 V		500		pC
ON-State NC, NO, COM capacitance	C_COM(ON)	V_COM= V_CC or GND	See Figure 17	25°C	5 V		370		pF
Digital input capacitance	C_I	V_IN = V_CC or GND	See Figure 17	25°C	5 V		2.6		pF
Bandwidth	BW	R_L = 50 Ω	See Figure 20	25°C	5 V		18.3		MHz
Off-state isolation	O_ISO	R_L = 50 Ω	f = 100 kHz, See Figure 21	25°C	5 V		–70		dB
Crosstalk	X_TALK	R_L = 50 Ω	f = 100 kHz, See Figure 22	25°C	5 V		–78		dB
Total harmonic distortion	THD	R_L = 600 Ω, C_L = 35 pF	f = 20 Hz to 20 kHz, See Figure 24	25°C	5 V		0.009		%
SUPPLY
Positive supply current	I_CC	V_COM and V_IN = V_CC or GND, V_NC or V_NO = floating		25°C	5.5 V		0.2	1.3	μA
		V_COM and V_IN = V_CC or GND, V_NC or V_NO = floating		–40°C to +125°C				3.5
		V_COM = V_CC – 5.5 V, V_IN = V_CC or GND, V_NC or V_NO = floating		–40°C to +125°C				5

(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(2) All unused digital inputs of the device must be held at V_CC or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report, SCBA004.