SCDS371E January   2018  – April 2019 TS5MP646

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified D-PHY Schematic
      2.      Simplified C-PHY Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-Off Protection
      2. 8.3.2 1.8-V Logic Compatible Inputs
      3. 8.3.3 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Disable Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 MIPI D-PHY Application
        2. 9.2.3.2 MIPI C-PHY Application
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

TS5MP646 scds371-on-resistance.gifFigure 7. On Resistance
TS5MP646 scds371-off-leakage.gifFigure 8. Off Leakage
TS5MP646 scds371-on-leakage.gifFigure 9. On Leakage
TS5MP646 scds371-t-switch-timing.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns.
2. CL includes probe and jig capacitance.
Figure 10. tSWITCH Timing
TS5MP646 scds371-t-on-and-t-off-timing-for-oe.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns.
2. CL includes probe and jig capacitance.
Figure 11. tON and tOFF Timing for OE
TS5MP646 scds371-off-isolation.gifFigure 12. Off Isolation
TS5MP646 scds371-crosstalk.gifFigure 13. Crosstalk
TS5MP646 scds371-bw-and-insertion-loss.gifFigure 14. Bandwidth and Insertion Loss
TS5MP646 scds371-t-pd-t-sk-intra-and-t-sk-inter-setup.gifFigure 15. tPD, tSKEW(INTRA) and tSKEW(INTER) Setup
TS5MP646 scds371-t-pd.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100 ps, tf = 100 ps.
2. CL includes probe and jig capacitance.
Figure 16. tPD
TS5MP646 scds371-tsk-instra.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100 ps, tf = 100 ps.
2. CL includes probe and jig capacitance.
Figure 17. tSKEW(INTRA)
TS5MP646 scds371-t-sk-inter.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100 ps, tf = 100 ps.
2. CL includes probe and jig capacitance.
3. tSKEW is the max skew between all channels. Diagram exaggerates tSKEW to show measurement technique
Figure 18. tSKEW(INTER)
TS5MP646 scds371-t-bbm.gif
1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns.
2. CL includes probe and jig capacitance.
Figure 19. tBBM