SLVSC89A June   2014  – July 2014 TSC2013-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements — I2C Standard Mode (ƒ(SCL) = 100 kHz)
    7. 6.7  Timing Requirements — I2C Fast Mode (ƒ(SCL) = 400 kHz)
    8. 6.8  Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 1.7 MHz)
    9. 6.9  Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz)
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Touch-Screen Operation
      2. 7.3.2 4-Wire Touch Screen Measurements
      3. 7.3.3 Analog-to-Digital Converter
        1. 7.3.3.1 Data Format
        2. 7.3.3.2 Reference
        3. 7.3.3.3 Variable Resolution
        4. 7.3.3.4 Conversion Clock and Conversion Time
        5. 7.3.3.5 Touch Detect
        6. 7.3.3.6 Preprocessing
          1. 7.3.3.6.1 Preprocessing—Median Value Filter and Averaging Value Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Controlled by TSC2013-Q1 and Initiated by TSC2013-Q1 (TSMode 1)
        1. 7.4.1.1 IX-IY Scan
        2. 7.4.1.2 X-Triplet, Y-Triplet, Z-Scan
      2. 7.4.2 Conversion Controlled by TSC2013-Q1 and Initiated by Host (TSMode 2)
      3. 7.4.3 Conversion Controlled by Host (TSMode 3)
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Fast or Standard Mode (F-S Mode)
        2. 7.5.1.2 I2C High-Speed Mode (Hs Mode)
      2. 7.5.2 Digital Interface
        1. 7.5.2.1 Address Byte
      3. 7.5.3 Control Byte
        1. 7.5.3.1 Touch-Screen Scan Function for XYZ or XY
      4. 7.5.4 Start a Write Cycle
      5. 7.5.5 Register Access
      6. 7.5.6 Communication Protocol
      7. 7.5.7 Register Reset
    6. 7.6 Register Maps
      1. 7.6.1 Register Content and Reset Values
      2. 7.6.2 Configuration and Status Registers
        1. 7.6.2.1 Configuration Register 0
          1. 7.6.2.1.1 Configuration Register 0 (address = 0) [reset = 4000h for read; 0000h for write]
        2. 7.6.2.2 Configuration Register 1 (address = Dh) [reset = 0000h]
        3. 7.6.2.3 Configuration Register 2 (address = Eh) [reset = 0000h]
        4. 7.6.2.4 Converter-Function Select Register (address = Fh) [reset = 0000h]
        5. 7.6.2.5 Status Register (address = 8h) [reset = 0004h]
      3. 7.6.3 Data Registers
        1. 7.6.3.1 X1, X2, IX, Y1, Y2, IY, Z1, Z2, and AUX registers (offset = see ) [reset = see ]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Auxiliary Measurement
      2. 8.1.2 Single IX or Single IY Measurement
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-On-Reset and Reset Consideration
          1. 8.2.2.1.1 Power-On Reset
          2. 8.2.2.1.2 Requesting a Minimal t(SNSVDD_OFF) Time
          3. 8.2.2.1.3 Requesting a Minimal t(SNSVDD_OFF_ramp) and t(SNSVDD_ON_ramp) Ramp
          4. 8.2.2.1.4 Hardware Reset
          5. 8.2.2.1.5 Software Reset
        2. 8.2.2.2 Power Up Considerations
          1. 8.2.2.2.1 Power-Off Cycles During Normal Operation
          2. 8.2.2.2.2 Supply Glitches During Normal Operation
          3. 8.2.2.2.3 TSC2013-Q1 Digital Pins
          4. 8.2.2.2.4 Suggested Hardware Reset During Power-On
        3. 8.2.2.3 Device Timing Setup and Use
          1. 8.2.2.3.1 Touch-Panel Driving Power
          2. 8.2.2.3.2 ADC Clock Effects
        4. 8.2.2.4 Panel Voltage Stabilization Time
        5. 8.2.2.5 Precharge and Sense Time
        6. 8.2.2.6 Single-Touch Operation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The following layout suggestions should obtain optimum performance from the TSC2013-Q1 device. However, many portable applications have conflicting requirements for power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low-power. This situation would mean less bypassing for the converter power and less concern regarding grounding. Still, each application is unique, so review the following suggestions carefully.

For optimum performance, take care with the physical layout of the TSC2013-Q1 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, and ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCL input.

With this in mind, power to the TSC2013-Q1 device should be clean and well-bypassed. Add a 0.1-μF ceramic bypass capacitor between (SNSVDD and AGND) or (I/OVDD and AGND). The circuit also requires a 0.1-μF decoupling capacitor between SNSVDD/VREF and AGND. Place these capacitors as close to the device as possible. The circuit may also require a 1-μF to 10-μF capacitor if the impedance of the connection between SNSVDD/VREF and the power supply is high. Short I/OVDD to the same supply plane as SNSVDD/VREF. Short both SNSVDD/VREF and I/OVDD to the analog power-supply plane.

The ADC architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input, which is of particular concern when the reference input is tied to the power supply for auxiliary input. Any noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered out by the built-in MAV filter, voltage variation as a result of line frequency (50 Hz or 60 Hz) can be difficult to remove. Avoid any active trace going under the analog pins listed in the table without shielding them by a ground or power plane.

Connect the AGND pin to a clean ground point. In many cases, this connection will be the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery-connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry.

In the specific case of use with a resistive touch screen, take care with the connection between the converter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or vibrations.

As indicated previously, noise can be a major source of error in touch-screen applications (for example, applications that require a backlit LCD panel). This electromagnetic interference (EMI) noise can coupled through the LCD panel to the touch screen and cause flickering of the converted ADC data. On can do several things to reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground, which couples the majority of noise to ground. Another way to filter out this type of noise is by using the TSC2013-Q1 built-in MAV filter (see the section). Filtering capacitors, from Y+, Y–, X+, and X– to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and requires longer panel voltage stabilization times, and also increases precharge and sense times for the PINTDAV circuitry of the TSC2013-Q1 device. The resistor value varies depending on the touch-screen sensor used. The internal 50-kΩ pullup resistor (R(IRQ)) may be adequate for most sensors.

10.2 Layout Example

layout_ex_slvsc89.gifFigure 57. TSC2013-Q1 Layout Example