SLOSEC9 September   2024 TSD5402-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements for I2C Interface Signals
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input and Preamplifier
      2. 6.3.2 Pulse-Width Modulator (PWM)
      3. 6.3.3 Gate Drive
      4. 6.3.4 Power FETs
      5. 6.3.5 Load Diagnostics
        1. 6.3.5.1 Load Diagnostics Sequence
        2. 6.3.5.2 Faults During Load Diagnostics
      6. 6.3.6 Protection and Monitoring
      7. 6.3.7 I2C Serial Communication Bus
        1. 6.3.7.1 I2C Bus Protocol
        2. 6.3.7.2 Random Write
        3. 6.3.7.3 Random Read
        4. 6.3.7.4 Sequential Read
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Control Pins
      2. 6.4.2 EMI Considerations
      3. 6.4.3 Operating Modes and Faults
  8. 7 Register Maps
    1. 7.1 I2C Address Register Definitions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Signal Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 HI-Z Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Signal Input
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Top Layer
        2. 8.4.2.2 Second Layer – Signal Layer
        3. 8.4.2.3 Third Layer – Power Layer
        4. 8.4.2.4 Bottom Layer – Ground Layer
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
      1. 11.1.1 Packaging Information
      2. 11.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OPERATING CURRENT
PVDD idle currentIn DRIVE mode, no signal present16mA
PVDD standby currentSTANDBY mode, HI-Z= 0 V520µA
OUTPUT POWER
Output power per channel4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C6W
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C8
Power efficiency4 Ω, P(O) = 8 W (10% THD)83%
OUTPUT PERFORMANCE
Noise voltage at outputG = 20 dB, zero input, and A-weighting65µV
Common-mode rejection ratiof = 1 kHz, 100 mVrms referenced to GND, G = 20 dB63dB
Power-supply rejection ratioPVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz75
Total harmonic distortion + noiseP(O) = 1 W, f = 1 kHz0.05%
Switching frequencySwitching frequency selectable for AM interference avoidance400kHz
500
Internal common-mode input bias voltageInternal bias applied to IN_N, IN_P pins3V
Voltage gain (VO / VIN)Source impedance = 0 Ω, register 0x03 bits 7–6 = 00192021dB
Source impedance = 0 Ω, register 0x03 bits 7–6 = 01252627
Source impedance = 0 Ω, register 0x03 bits 7–6 = 10313233
Source impedance = 0 Ω, register 0x03 bits 7–6 = 11353637
PWM OUTPUT STAGE
FET drain-to-source resistanceTJ = 25°C180mΩ
Output offset voltageZero input signal, G = 20 dB±25mV
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set19.52122.5V
PVDD overvoltage-shutdown hysteresis0.6V
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set3.644.4V
PVDD undervoltage-shutdown hysteresis0.25V
BYP
BYP pin voltage6.46.97.4V
POWER-ON RESET (POR)
PVDD voltage for POR4.1V
PVDD recovery hysteresis voltage for POR0.3V
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown155170°C
Junction temperature overtemperature shutdown hystersis15°C
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current)2.4A
STANDBY PIN
STANDBY pin current0.10.2µA
DC DETECT
DC detect threshold2.9V
DC detect step response time700ms
FAULT REPORT
FAULT pin output voltage for logic-level high (open-drain logic output)External 47-kΩ pullup resistor to 3.3 V2.4V
FAULT pin output voltage for logic-level low (open-drain logic output)External 47-kΩ pullup resistor to 3.3 V0.5V
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or ground200Ω
Open-circuit detection thresholdIncluding load wires7095120Ω
Short-circuit detection thresholdIncluding load wires0.91.21.5Ω
I2C
SDA pin output voltage for logic-level highR(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V2.4V
SDA pin output voltage for logic-level low3-mA sink current0.4V
Capacitance for SCL and SDA pins10pF
Capacitance for SDA pinSTANDBY mode30pF