SLVSH75A August   2023  – January 2024 TSM24CA

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - JEDEC Specifications
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
  8. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBZ|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 100nA -24 24 V
ILEAK Leakage current at VRWM VIO = 24V, I/O to GND and GND to I/O 25 75 nA
VBR Breakdown voltage, I/O to GND and GND to I/O (1) IIO = 10mA 25.5 V
VCLAMP Surge clamping voltage, tp = 8/20µs (3) IPP = 24A, I/O to GND and GND to I/O 40 V
CLINE Line capacitance, IO to GND VIO = 0V, f = 1MHz 12 pF
(1) VBR is defined as the voltage obtained at 10mA when sweeping the voltage up, before the device latches into the snapback state
(2) Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5